sun/io/fd.c

6296 		struct cheerio_dma_reg *dma_reg;
6297 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6298 		ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr, count);
6300 		struct sb_dma_reg *dma_reg;
6302 		dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6306 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT],
6311 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT],
6316 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT],
6321 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT],
6343 		struct cheerio_dma_reg *dma_reg;
6344 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6345 		retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dbcr);
6347 		struct sb_dma_reg *dma_reg;
6348 		dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6352 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_0WCNT]);
6356 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_1WCNT]);
6360 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_2WCNT]);
6364 			    (ushort_t *)&dma_reg->sb_dma_regs[DMA_3WCNT]);
6388 		struct cheerio_dma_reg *dma_reg;
6389 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6390 		ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, DCSR_RESET);
6393 		ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, 0);
6395 		struct sb_dma_reg *dma_reg;
6396 		dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6397 		ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MASK],
6413 		struct cheerio_dma_reg *dma_reg;
6414 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6415 		retval = ddi_get32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr);
6430 		struct cheerio_dma_reg *dma_reg;
6431 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6432 		ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dacr, address);
6434 		struct sb_dma_reg *dma_reg;
6435 		dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6439 				    &dma_reg->sb_dma_regs[DMA_0PAGE],
6442 				    &dma_reg->sb_dma_regs[DMA_0HPG],
6445 				    (ushort_t *)&dma_reg->sb_dma_regs[DMA_0ADR],
6450 				    &dma_reg->sb_dma_regs[DMA_1PAGE],
6453 				    &dma_reg->sb_dma_regs[DMA_1HPG],
6456 				    (ushort_t *)&dma_reg->sb_dma_regs[DMA_1ADR],
6461 				    &dma_reg->sb_dma_regs[DMA_2PAGE],
6464 				    &dma_reg->sb_dma_regs[DMA_2HPG],
6467 				    (ushort_t *)&dma_reg->sb_dma_regs[DMA_2ADR],
6472 				    &dma_reg->sb_dma_regs[DMA_3PAGE],
6475 				    &dma_reg->sb_dma_regs[DMA_3HPG],
6478 				    (ushort_t *)&dma_reg->sb_dma_regs[DMA_3ADR],
6500 		struct cheerio_dma_reg *dma_reg;
6501 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6503 			ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr,
6506 			ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr,
6511 		struct sb_dma_reg *dma_reg;
6512 		dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6521 		ddi_put8(fdc->c_handlep_dma, &dma_reg->sb_dma_regs[DMAC1_MODE],
6525 		    &dma_reg->sb_dma_regs[DMAC1_ALLMASK], ~chn_mask);
6540 		struct cheerio_dma_reg *dma_reg;
6541 		dma_reg = (struct cheerio_dma_reg *)fdc->c_dma_regs;
6542 		ddi_put32(fdc->c_handlep_dma, &dma_reg->fdc_dcsr, val);
6549 	struct sb_dma_reg *dma_reg;
6550 	dma_reg = (struct sb_dma_reg *)fdc->c_dma_regs;
6553 	    &dma_reg->sb_dma_regs[DMAC1_ALLMASK], NULL);