Lines Matching refs:g2
645 lduw [%o2 + CPU_MMU_IDX], %g2 ! %g2 = mmu index
672 sllx %g2, SFMMU_MMU_CTX_SHIFT, %g2
673 add %o0, %g2, %g2 ! %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
678 * %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
683 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
731 * %g2 = &sfmmu_ctxs[mmuid] - SFMMU_CTXS
734 SFMMU_MMUID_GNUM_CNUM(%g2, %g5, %g6, %g4)
773 * %g2 = &sfmmu_ctx_t[mmuid] - SFMMU_CTXS;
820 stx %o4, [%g2 + SFMMU_CTXS]
867 ldx [%o1], %g2 /* modified */
868 cmp %g2, %g3 /* is modified = current? */
871 casx [%o2], %g1, %g2
872 cmp %g1, %g2
884 ldx [%o1], %g2 /* modified */
887 cmp %g3, %g2 /* is modified = current? */
891 casx [%o2], %g1, %g2
893 cmp %g1, %g2
897 stx %g2, [%o0] /* report "current" value */
1472 TSB_UPDATE(%o0, %o2, %o1, %g1, %g2, locked_tsb_l8)
1521 GET_KPM_TSBE_POINTER(%o2, %g2, %g1, %o3, %o4)
1522 /* %g2 = tsbep, %g1 clobbered */
1526 TSB_UPDATE(%g2, %o1, %g1, %o3, %o4, locked_tsb_l9)
1553 GET_KPM_TSBE_POINTER(%o1, %g2, %g1, %o3, %o4)
1554 /* %g2 = tsbep, %g1 clobbered */
1558 TSB_INVALIDATE(%g2, %g1, %o3, %o4, %o1, kpm_tsbinval)
1578 TTETOPFN(%g1, %o1, sfmmu_ttetopfn_l1, %g2, %g3, %g4)
1728 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g6, %g4)
1736 mov %g5, %g2
1755 * g2 = tag access reg
1769 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g6)
1777 mov %g5, %g2
1785 * g2 = tag access reg
1798 GET_MMU_BOTH_TAGACC(%g5 /*dtag*/, %g2 /*itag*/, %g4, %g3)
1803 mov %g5, %g2
1810 /* g1 = TL0 handler, g2 = tagacc, g3 = trap type */
1854 rdpr %tt, %g2
1865 rdpr %tt, %g2
1868 and %g2, WTRAP_TTMASK, %g4
1934 CPU_INDEX(%g1, %g2)
1935 set cpu_core, %g2
1937 add %g1, %g2, %g1
1938 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
1939 andcc %g2, CPU_DTRACE_NOFAULT, %g0
1941 or %g2, CPU_DTRACE_BADADDR, %g2
1942 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
1947 TSTAT_CHECK_TL1(1f, %g1, %g2)
1951 GET_MMU_D_TAGACC(%g2 /* tagacc */, %g4 /*scratch*/)
1954 * g2=tagacc g3.l=type g3.h=0
2423 * g2 = tag access register (ro)
2430 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2440 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
2459 * g2 = tag access register (ro)
2465 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2466 /* %g1 = first TSB entry ptr now, %g2 preserved */
2472 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2473 /* %g3 = second TSB entry ptr now, %g2 preserved */
2482 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2483 /* %g3 = second TSB entry ptr now, %g2 preserved */
2488 mov %g2, %g7
2507 * %g2 = tag access register (used)
2524 iktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2530 srlx %g2, MMU_PAGESHIFT4M, %g3 ! use 4m virt-page as TSB index
2536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2553 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2569 * %g2 = tag access register (used)
2579 KPM_TLBMISS_STAT_INCR(%g2, %g4, %g5, %g6, kpmtlbm_stat_out)
2592 dktsb: sllx %g2, 64-(TAGACC_SHIFT + TSB_START_SIZE + RUNTIME_PATCH), %g1
2601 srlx %g2, TAG_VALO_SHIFT, %g6 ! make tag to compare
2606 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2619 brlz,pn %g2, sfmmu_kpm_dtsb_miss_small
2628 * %g2 = tag access register (we still need it)
2630 srlx %g2, MMU_PAGESHIFT4M, %g3
2649 srlx %g2, TAG_VALO_SHIFT, %g6 ! make tag to compare
2657 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
2677 * g2 = tag access register
2681 cmp %g2, %g0
2695 * g2 = tag access register
2714 * g2 = tag access register
2738 * g2 = tag access register
2745 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2749 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2751 srlx %g2, TAG_VALO_SHIFT, %g7
2777 * g2 = tag access register
2789 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2795 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2801 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2810 mov %g2, %g6 /* GET_2ND_TSBE_PTR clobbers tagacc */
2814 srlx %g2, TAG_VALO_SHIFT, %g7
2834 * g2 = tag access register
2855 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2865 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2875 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2885 * g2 = tag access register
2903 GET_4TH_TSBE_PTR(%g2, %g6, %g4, %g5)
2913 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2925 GET_3RD_TSBE_PTR(%g2, %g6, %g4, %g5)
2936 srax %g2, PREDISM_BASESHIFT, %g6 /* g6 > 0 : ISM predicted */
2943 * g2 = tag access register
2949 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
2955 * g2 = tag access reg
2968 * g2 = tag access reg
2981 * g2 = tag access reg
2988 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
2989 /* %g2 is okay, no need to reload, %g3 = second tsbe ptr */
2992 GET_2ND_TSBE_PTR(%g2, %g7, %g3, %g4, %g5, sfmmu_udtlb)
2993 /* %g2 clobbered, %g3 =second tsbe ptr */
2994 mov MMU_TAG_ACCESS, %g2
2995 ldxa [%g2]ASI_DMMU, %g2
2998 srlx %g2, TAG_VALO_SHIFT, %g7
3014 * g2 = tag access register
3046 sllx %g2, TAGACC_CTX_LSHIFT, %g3
3064 ISM_CHECK(%g2, %g6, %g3, %g4, %g5, %g7, %g1, tsb_l1, tsb_ism)
3069 * %g2 = (pseudo) tag access
3082 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3088 sllx %g2, TAGACC_CTX_LSHIFT, %g5
3111 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3117 sllx %g2, TAGACC_CTX_LSHIFT, %g5
3128 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3134 sllx %g2, TAGACC_CTX_LSHIFT, %g5
3149 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3167 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3175 * g2 = tagacc
3192 * g2 = tagacc
3195 sllx %g2, TAGACC_CTX_LSHIFT, %g5
3202 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3217 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3231 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3246 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3261 GET_SHME_TTE(%g2, %g7, %g3, %g4, %g6, %g1,
3284 SAVE_CTX1(%g7, %g2, %g1, tsb_shmel)
3305 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
3344 MMU_FAULT_STATUS_AREA(%g2)
3351 add %g2, MMFSA_D_, %g2
3353 ldx [%g2 + MMFSA_CTX_], %g7
3355 ldx [%g2 + MMFSA_ADDR_], %g2
3356 mov %g2, %g5 ! load the fault addr for later use
3357 srlx %g2, TTARGET_VA_SHIFT, %g2
3358 or %g2, %g7, %g2
3363 ldxa [%g0]ASI_IMMU, %g2
3364 ldxa [%g0]ASI_DMMU, %g2
3372 srlx %g2, TTARGET_CTX_SHIFT, %g7
3419 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l3)
3431 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3435 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3462 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l4)
3475 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3479 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3495 * g2 = tagtarget
3517 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l5) /* update TSB */
3519 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3533 TSB_UPDATE_TL_PN(%g1, %g5, %g2, %g4, %g7, %g3, locked_tsb_l6) /* update TSB */
3536 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3563 TSB_UPDATE_TL(%g1, %g3, %g2, %g4, %g7, %g6, locked_tsb_l7)
3573 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3577 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4)
3586 * g2 = vaddr + ctx(or ctxtype (sun4v)) aka (pseudo-)tag access
3601 and %g2, %g1, %g4 /* g4 = ctx number */
3602 andn %g2, %g1, %g1 /* g1 = tlb miss vaddr */
3603 sub %g1, %g3, %g2 /* g2 = offset in ISM seg */
3604 or %g2, %g4, %g2 /* g2 = (pseudo-)tagacc */
3623 * g2 = tagacc w/ISM vaddr (offset in ISM seg)
3643 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT32M,
3662 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT256M,
3674 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT4M,
3688 GET_TTE(%g2, %g7, %g3, %g4, %g6, %g1, MMU_PAGESHIFT64K,
3727 ldxa [%g4]ASI_DMMU, %g2
3729 move %icc, %g5, %g2
3731 move %icc, %g5, %g2
3732 sllx %g2, TAGACC_CTX_LSHIFT, %g4
3739 srlx %g2, MMU_PAGESHIFT, %g4
3747 TSTAT_CHECK_TL1(2f, %g1, %g2)
3748 rdpr %tt, %g2
3749 cmp %g2, FAST_PROT_TT
3764 CPU_INDEX(%g1, %g2)
3765 set cpu_core, %g2
3767 add %g1, %g2, %g1
3768 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3769 andcc %g2, CPU_DTRACE_NOFAULT, %g0
3771 or %g2, CPU_DTRACE_BADADDR, %g2
3772 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3781 TSTAT_CHECK_TL1(4f, %g1, %g2)
3791 CPU_INDEX(%g1, %g2)
3792 set cpu_core, %g2
3794 add %g1, %g2, %g1
3795 lduh [%g1 + CPUC_DTRACE_FLAGS], %g2
3796 andcc %g2, CPU_DTRACE_NOFAULT, %g0
3798 or %g2, CPU_DTRACE_BADADDR, %g2
3799 stuh %g2, [%g1 + CPUC_DTRACE_FLAGS]
3808 rdpr %tstate, %g2
3809 btst TSTATE_PRIV, %g2
3840 TSTAT_CHECK_TL1(2f, %g1, %g2);
3848 MMU_FAULT_STATUS_AREA(%g2)
3850 ldx [%g2 + MMFSA_I_CTX], %g3
3853 ldx [%g2 + MMFSA_I_CTX], %g3
3854 ldx [%g2 + MMFSA_D_CTX], %g3
3857 mov MMU_TAG_ACCESS, %g2
3859 ldxa [%g2]ASI_IMMU, %g3
3860 ldxa [%g2]ASI_DMMU, %g3
3869 TSTAT_CHECK_TL1(sfmmu_mmu_trap, %g1, %g2)
3947 GET_TTE(%o0, %o4, %g1, %g2, %o5, %g4, %g6, %g5, %g3,
3956 * g2 = tte pa
3964 TTETOPFN(%g1, %o0, vatopfn_l2, %g2, %g3, %g4)
4011 * g2 = tte pa
4099 TTETOPFN(%g3, %o0, kvaszc2pfn_l2, %g2, %g4, %g5)
4196 * g2 = tag access register
4216 cmp %g2, %g7
4219 cmp %g2, %g5
4240 * g2 = tag access register
4248 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4249 srax %g4, %g3, %g2 /* which alias range (r) */
4250 brnz,pn %g2, sfmmu_kpm_exception /* if (r != 0) goto C handler */
4251 srlx %g4, MMU_PAGESHIFT, %g2 /* %g2 = pfn */
4257 * g2=pfn
4260 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmp2m)
4267 * g2=pfn g3=mseg_pa
4271 srlx %g2, %g5, %g4
4278 * g2=pfn g3=mseg_pa g4=inx
4297 * g2=pfn g3=mseg_pa g4=offset g5=kp g7=kpmp_table_sz
4307 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4314 * g1=kp_refcntc_pa g2=pfn g5=hashinx
4323 * g1=kp_pa g2=pfn g3=hlck_pa
4340 sllx %g2, MMU_PAGESHIFT, %g4
4343 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4347 * g1=kp_pa g2=ttarget g3=hlck_pa g4=kpmtsbp4m g5=tte g6=kpmtsbm_area
4382 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4384 DTLB_STUFF(%g5, %g1, %g2, %g4, %g6)
4420 * g2 = tag access register
4442 cmp %g2, %g7
4445 cmp %g2, %g5
4466 * g2 = tag access register
4478 sub %g2, %g7, %g4 /* paddr = vaddr-kpm_vbase */
4484 srlx %g2, MMU_PAGESHIFT, %g1 /* vaddr >> MMU_PAGESHIFT */
4502 * g2 = tag access register
4510 srlx %g4, MMU_PAGESHIFT, %g2 /* g2 = pfn */
4516 * g2=pfn g6=per-CPU kpm tsbmiss area
4520 PAGE_NUM2MEMSEG_NOLOCK_PA(%g2, %g3, %g6, %g4, %g5, %g7, kpmtsbmsp2m)
4527 * g2=pfn g3=mseg_pa g6=per-CPU kpm tsbmiss area
4530 sub %g2, %g7, %g4
4535 * g2=pfn g3=mseg_pa g4=inx g6=per-CPU tsbmiss area
4550 * g2=pfn g3=mseg_pa g4=inx g5=ksp
4561 * g2=pfn g3=mseg_pa g4=offset g5=hashinx
4570 * g1=ksp_pa g2=pfn g5=hashinx
4579 * g1=ksp_pa g2=pfn g3=hlck_pa
4586 sllx %g2, MMU_PAGESHIFT, %g4
4589 GET_MMU_D_TTARGET(%g2, %g7) /* %g2 = ttarget */
4593 * g1=ksp_pa g2=ttarget g3=hlck_pa g4=ktsbp g5=tte (non-cacheable)
4626 TSB_INSERT_UNLOCK_ENTRY(%g4, %g5, %g2, %g7)
4628 DTLB_STUFF(%g5, %g2, %g4, %g5, %g6)
4784 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) ! %g2 = ptagacc, %g3 = ctx type
4788 * %g2 = tagacc register (needed for sfmmu_tsb_miss_tt)
4799 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4808 mov %g2, %g7 ! TSB pointer macro clobbers tagacc
4826 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5)
4827 /* %g1 = first TSB entry ptr now, %g2 preserved */
4833 GET_2ND_TSBE_PTR(%g2, %g3, %g4, %g5)
4834 /* %g3 = second TSB entry ptr now, %g2 preserved */
4850 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3)