io/drm/radeon_drv.h

160 #define	GET_RING_HEAD(dev_priv)	\
161 	(dev_priv->writeback_works ? \
162 	DRM_READ32((dev_priv)->ring_rptr, 0) : \
165 #define	SET_RING_HEAD(dev_priv, val)	\
166 	DRM_WRITE32((dev_priv)->ring_rptr, 0, (val))
333 #define	RADEON_CHECK_OFFSET(dev_priv, off) \
334 	(((off >= dev_priv->fb_location) && \
335 	(off <= (dev_priv->fb_location + dev_priv->fb_size - 1))) || \
336 	((off >= dev_priv->gart_vm_start) && \
337 	(off <= (dev_priv->gart_vm_start + dev_priv->gart_size - 1))))
353 extern int radeon_wait_ring(drm_radeon_private_t *dev_priv, int n);
355 extern int radeon_do_cp_idle(drm_radeon_private_t *dev_priv);
497 #define	GET_SCRATCH(x)	(dev_priv->writeback_works ? \
498     DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x)) : \
1007 	DRM_READ32(dev_priv->mmio, (reg))
1009 	DRM_WRITE32(dev_priv->mmio, (reg), (val))
1011 	DRM_READ8(dev_priv->mmio, (reg))
1013 	DRM_WRITE8(dev_priv->mmio, (reg), (val))
1093 #define	RING_SPACE_TEST_WITH_RETURN(dev_priv)				\
1095 	if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) {		\
1096 		u32 head = GET_RING_HEAD(dev_priv);			\
1097 		if (head == dev_priv->ring.tail)			\
1098 			dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE;	\
1102 #define	VB_AGE_TEST_WITH_RETURN(dev_priv)				\
1104 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
1106 		int __ret = radeon_do_cp_idle(dev_priv);		\
1135 	if (dev_priv->ring.space <= (n) * sizeof (u32)) {		\
1137 		(void) radeon_wait_ring(dev_priv, (n) * sizeof (u32));	\
1139 	_nr = n; dev_priv->ring.space -= (n) * sizeof (u32);		\
1140 	ring = dev_priv->ring.start;					\
1141 	write = dev_priv->ring.tail;					\
1142 	mask = dev_priv->ring.tail_mask;				\
1146 	if (((dev_priv->ring.tail + _nr) & mask) != write) {		\
1150 			((dev_priv->ring.tail + _nr) & mask),		\
1153 		dev_priv->ring.tail = write;				\
1163 	GET_RING_HEAD(dev_priv);					\
1164 	RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);		\