Lines Matching defs:dev_priv
827 drm_radeon_private_t *dev_priv = dev->dev_private;
833 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
840 static void radeon_status(drm_radeon_private_t *dev_priv)
865 static int radeon_do_pixcache_flush(drm_radeon_private_t *dev_priv)
870 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
876 for (i = 0; i < dev_priv->usec_timeout; i++) {
886 radeon_status(dev_priv);
891 static int radeon_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
895 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
897 for (i = 0; i < dev_priv->usec_timeout; i++) {
907 dev_priv->usec_timeout);
909 radeon_status(dev_priv);
914 static int radeon_do_wait_for_idle(drm_radeon_private_t *dev_priv)
918 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
920 ret = radeon_do_wait_for_fifo(dev_priv, 64);
924 for (i = 0; i < dev_priv->usec_timeout; i++) {
927 (void) radeon_do_pixcache_flush(dev_priv);
934 dev_priv->usec_timeout);
937 radeon_status(dev_priv);
947 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
951 (void) radeon_do_wait_for_idle(dev_priv);
955 if (dev_priv->microcode_version == UCODE_R200) {
963 } else if (dev_priv->microcode_version == UCODE_R300) {
987 static void radeon_do_cp_flush(drm_radeon_private_t *dev_priv)
1001 radeon_do_cp_idle(drm_radeon_private_t *dev_priv)
1014 return (radeon_do_wait_for_idle(dev_priv));
1018 static void radeon_do_cp_start(drm_radeon_private_t *dev_priv)
1022 (void) radeon_do_wait_for_idle(dev_priv);
1024 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1026 dev_priv->cp_running = 1;
1043 static void radeon_do_cp_reset(drm_radeon_private_t *dev_priv)
1050 SET_RING_HEAD(dev_priv, cur_read_ptr);
1051 dev_priv->ring.tail = cur_read_ptr;
1059 static void radeon_do_cp_stop(drm_radeon_private_t *dev_priv)
1065 dev_priv->cp_running = 0;
1071 drm_radeon_private_t *dev_priv = dev->dev_private;
1075 (void) radeon_do_pixcache_flush(dev_priv);
1114 radeon_do_cp_reset(dev_priv);
1117 dev_priv->cp_running = 0;
1126 radeon_cp_init_ring_buffer(drm_device_t *dev, drm_radeon_private_t *dev_priv)
1138 if (!dev_priv->new_memmap)
1140 ((dev_priv->gart_vm_start - 1) & 0xffff0000) |
1141 (dev_priv->fb_location >> 16));
1144 if (dev_priv->flags & RADEON_IS_AGP) {
1147 (((dev_priv->gart_vm_start - 1 +
1148 dev_priv->gart_size) & 0xffff0000) |
1149 (dev_priv->gart_vm_start >> 16)));
1151 ring_start = dev_priv->cp_ring->offset -
1152 dev->agp->base + dev_priv->gart_vm_start;
1155 ring_start = (dev_priv->cp_ring->offset -
1157 dev_priv->gart_vm_start);
1167 SET_RING_HEAD(dev_priv, cur_read_ptr);
1168 dev_priv->ring.tail = cur_read_ptr;
1171 if (dev_priv->flags & RADEON_IS_AGP) {
1173 dev_priv->ring_rptr->offset -
1174 dev->agp->base + dev_priv->gart_vm_start);
1181 tmp_ofs = dev_priv->ring_rptr->offset -
1194 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1196 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1200 dev_priv->writeback_works = 0;
1213 dev_priv->scratch = ((__volatile__ u32 *)
1214 dev_priv->ring_rptr->handle +
1223 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1224 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1226 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1228 dev_priv->sarea_priv->last_dispatch);
1230 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1231 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1233 (void) radeon_do_wait_for_idle(dev_priv);
1244 static void radeon_test_writeback(drm_radeon_private_t *dev_priv)
1253 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1256 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1257 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1263 tmp = dev_priv->usec_timeout;
1265 if (tmp < dev_priv->usec_timeout) {
1266 dev_priv->writeback_works = 1;
1269 dev_priv->writeback_works = 0;
1273 dev_priv->writeback_works = 0;
1284 dev_priv->writeback_works = 0;
1287 if (!dev_priv->writeback_works) {
1300 static void radeon_set_pciegart(drm_radeon_private_t *dev_priv, int on)
1302 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1306 dev_priv->gart_vm_start,
1307 (long)dev_priv->gart_info.bus_addr,
1308 dev_priv->gart_size);
1310 dev_priv->gart_vm_start);
1312 dev_priv->gart_info.bus_addr);
1314 dev_priv->gart_vm_start);
1316 dev_priv->gart_vm_start + dev_priv->gart_size - 1);
1329 static void radeon_set_pcigart(drm_radeon_private_t *dev_priv, int on)
1333 if (dev_priv->flags & RADEON_IS_PCIE) {
1334 radeon_set_pciegart(dev_priv, on);
1345 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1348 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1349 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start +
1350 dev_priv->gart_size - 1);
1363 drm_radeon_private_t *dev_priv = dev->dev_private;
1366 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1373 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1375 dev_priv->flags &= ~RADEON_IS_AGP;
1376 } else if (!(dev_priv->flags &
1380 dev_priv->flags |= RADEON_IS_AGP;
1383 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1389 dev_priv->usec_timeout = init->usec_timeout;
1390 if (dev_priv->usec_timeout < 1 ||
1391 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1398 dev_priv->microcode_version = UCODE_R200;
1401 dev_priv->microcode_version = UCODE_R300;
1404 dev_priv->microcode_version = UCODE_R100;
1407 dev_priv->do_boxes = 0;
1408 dev_priv->cp_mode = init->cp_mode;
1424 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1428 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1431 dev_priv->front_offset = init->front_offset;
1432 dev_priv->front_pitch = init->front_pitch;
1433 dev_priv->back_offset = init->back_offset;
1434 dev_priv->back_pitch = init->back_pitch;
1438 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1442 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1445 dev_priv->depth_offset = init->depth_offset;
1446 dev_priv->depth_pitch = init->depth_pitch;
1454 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1455 (dev_priv->color_fmt << 10) |
1456 (dev_priv->microcode_version ==
1459 dev_priv->depth_clear.rb3d_zstencilcntl =
1460 (dev_priv->depth_fmt |
1467 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1481 dev_priv->ring_offset = init->ring_offset;
1482 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1483 dev_priv->buffers_offset = init->buffers_offset;
1484 dev_priv->gart_textures_offset = init->gart_textures_offset;
1486 if (!dev_priv->sarea) {
1492 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1493 if (!dev_priv->cp_ring) {
1499 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1500 if (!dev_priv->ring_rptr) {
1516 dev_priv->gart_textures =
1518 if (!dev_priv->gart_textures) {
1526 dev_priv->sarea_priv = (drm_radeon_sarea_t *)(uintptr_t)
1527 ((u8 *)(uintptr_t)dev_priv->sarea->handle +
1531 if (dev_priv->flags & RADEON_IS_AGP) {
1532 drm_core_ioremap(dev_priv->cp_ring, dev);
1533 drm_core_ioremap(dev_priv->ring_rptr, dev);
1535 if (!dev_priv->cp_ring->handle ||
1536 !dev_priv->ring_rptr->handle ||
1541 dev_priv->cp_ring->handle,
1542 dev_priv->ring_rptr->handle,
1550 dev_priv->cp_ring->handle =
1551 (void *)(intptr_t)dev_priv->cp_ring->offset;
1552 dev_priv->ring_rptr->handle =
1553 (void *)(intptr_t)dev_priv->ring_rptr->offset;
1557 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1558 dev_priv->cp_ring->handle);
1559 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1560 dev_priv->ring_rptr->handle);
1565 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) &
1567 dev_priv->fb_size =
1569 - dev_priv->fb_location;
1571 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1572 ((dev_priv->front_offset + dev_priv->fb_location) >> 10));
1574 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1575 ((dev_priv->back_offset + dev_priv->fb_location) >> 10));
1577 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1578 ((dev_priv->depth_offset + dev_priv->fb_location) >> 10));
1580 dev_priv->gart_size = init->gart_size;
1583 if (dev_priv->new_memmap) {
1594 if (dev_priv->flags & RADEON_IS_AGP) {
1597 if ((base + dev_priv->gart_size - 1) >=
1598 dev_priv->fb_location &&
1599 base < (dev_priv->fb_location +
1600 dev_priv->fb_size - 1)) {
1609 base = dev_priv->fb_location + dev_priv->fb_size;
1610 if (base < dev_priv->fb_location ||
1611 ((base + dev_priv->gart_size) &
1613 base = dev_priv->fb_location -
1614 dev_priv->gart_size;
1616 dev_priv->gart_vm_start = base & 0xffc00000u;
1617 if (dev_priv->gart_vm_start != base)
1619 base, dev_priv->gart_vm_start);
1622 dev_priv->gart_vm_start = dev_priv->fb_location +
1627 if (dev_priv->flags & RADEON_IS_AGP)
1628 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset -
1629 dev->agp->base + dev_priv->gart_vm_start);
1632 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset -
1633 (unsigned long)dev->sg->virtual + dev_priv->gart_vm_start);
1635 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1636 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1637 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1638 dev_priv->gart_buffers_offset);
1640 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1641 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle +
1643 dev_priv->ring.size = init->ring_size;
1644 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1646 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof (u32)) - 1;
1648 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1651 if (dev_priv->flags & RADEON_IS_AGP) {
1653 radeon_set_pcigart(dev_priv, 0);
1658 if (dev_priv->pcigart_offset) {
1659 dev_priv->gart_info.bus_addr =
1660 dev_priv->pcigart_offset + dev_priv->fb_location;
1661 dev_priv->gart_info.mapping.offset =
1662 dev_priv->gart_info.bus_addr;
1663 dev_priv->gart_info.mapping.size =
1666 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1667 dev_priv->gart_info.addr =
1668 dev_priv->gart_info.mapping.handle;
1670 dev_priv->gart_info.is_pcie =
1671 !!(dev_priv->flags & RADEON_IS_PCIE);
1672 dev_priv->gart_info.gart_table_location =
1676 dev_priv->gart_info.addr, dev_priv->pcigart_offset);
1678 dev_priv->gart_info.gart_table_location =
1680 dev_priv->gart_info.addr = NULL;
1681 dev_priv->gart_info.bus_addr = 0;
1682 if (dev_priv->flags & RADEON_IS_PCIE) {
1690 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1697 radeon_set_pcigart(dev_priv, 1);
1700 radeon_cp_load_microcode(dev_priv);
1701 radeon_cp_init_ring_buffer(dev, dev_priv);
1703 dev_priv->last_buf = 0;
1706 radeon_test_writeback(dev_priv);
1713 drm_radeon_private_t *dev_priv = dev->dev_private;
1724 if (dev_priv->flags & RADEON_IS_AGP) {
1725 if (dev_priv->cp_ring != NULL) {
1726 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1727 dev_priv->cp_ring = NULL;
1729 if (dev_priv->ring_rptr != NULL) {
1730 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1731 dev_priv->ring_rptr = NULL;
1741 if (dev_priv->gart_info.bus_addr) {
1743 radeon_set_pcigart(dev_priv, 0);
1744 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1748 if (dev_priv->gart_info.gart_table_location ==
1750 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1751 dev_priv->gart_info.addr = 0;
1755 (void) memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1770 drm_radeon_private_t *dev_priv = dev->dev_private;
1772 if (!dev_priv) {
1780 if (dev_priv->flags & RADEON_IS_AGP) {
1782 radeon_set_pcigart(dev_priv, 0);
1787 radeon_set_pcigart(dev_priv, 1);
1790 radeon_cp_load_microcode(dev_priv);
1791 radeon_cp_init_ring_buffer(dev, dev_priv);
1862 drm_radeon_private_t *dev_priv = dev->dev_private;
1866 if (dev_priv->cp_running) {
1869 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1871 dev_priv->cp_mode);
1875 radeon_do_cp_start(dev_priv);
1889 drm_radeon_private_t *dev_priv = dev->dev_private;
1897 if (!dev_priv->cp_running)
1905 radeon_do_cp_flush(dev_priv);
1913 ret = radeon_do_cp_idle(dev_priv);
1923 radeon_do_cp_stop(dev_priv);
1934 drm_radeon_private_t *dev_priv = dev->dev_private;
1937 if (dev_priv) {
1938 if (dev_priv->cp_running) {
1940 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1957 radeon_do_cp_stop(dev_priv);
1963 if (dev_priv->mmio)
1966 if (dev_priv->mmio) { /* remove all surfaces */
1977 radeon_mem_takedown(&(dev_priv->gart_heap));
1978 radeon_mem_takedown(&(dev_priv->fb_heap));
1991 drm_radeon_private_t *dev_priv = dev->dev_private;
1995 if (!dev_priv) {
2000 radeon_do_cp_reset(dev_priv);
2003 dev_priv->cp_running = 0;
2013 drm_radeon_private_t *dev_priv = dev->dev_private;
2017 return (radeon_do_cp_idle(dev_priv));
2079 drm_radeon_private_t *dev_priv = dev->dev_private;
2085 if (++dev_priv->last_buf >= dma->buf_count)
2086 dev_priv->last_buf = 0;
2088 start = dev_priv->last_buf;
2090 for (t = 0; t < dev_priv->usec_timeout; t++) {
2098 dev_priv->stats.requested_bufs++;
2107 dev_priv->stats.freelist_loops++;
2120 drm_radeon_private_t *dev_priv = dev->dev_private;
2125 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2127 if (++dev_priv->last_buf >= dma->buf_count)
2128 dev_priv->last_buf = 0;
2130 start = dev_priv->last_buf;
2131 dev_priv->stats.freelist_loops++;
2139 dev_priv->stats.requested_bufs++;
2155 drm_radeon_private_t *dev_priv = dev->dev_private;
2158 dev_priv->last_buf = 0;
2170 radeon_wait_ring(drm_radeon_private_t *dev_priv, int n)
2172 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2174 u32 last_head = GET_RING_HEAD(dev_priv);
2176 for (i = 0; i < dev_priv->usec_timeout; i++) {
2177 u32 head = GET_RING_HEAD(dev_priv);
2185 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2197 radeon_status(dev_priv);
2307 drm_radeon_private_t *dev_priv;
2310 dev_priv = drm_alloc(sizeof (drm_radeon_private_t), DRM_MEM_DRIVER);
2311 if (dev_priv == NULL)
2314 (void) memset(dev_priv, 0, sizeof (drm_radeon_private_t));
2315 dev->dev_private = (void *)dev_priv;
2316 dev_priv->flags = (int)flags;
2326 dev_priv->flags |= RADEON_HAS_HIERZ;
2334 dev_priv->flags |= RADEON_IS_AGP;
2336 dev_priv->flags |= RADEON_IS_PCIE;
2338 dev_priv->flags |= RADEON_IS_PCI;
2352 drm_radeon_private_t *dev_priv = dev->dev_private;
2354 /* dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; */
2358 _DRM_READ_ONLY, &dev_priv->mmio);
2380 drm_radeon_private_t *dev_priv = dev->dev_private;
2383 drm_free(dev_priv, sizeof (*dev_priv), DRM_MEM_DRIVER);