io/drm/i915_irq.c

66 igdng_enable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq)
68 	if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != 0)) {
69 		dev_priv->gt_irq_mask_reg &= ~mask;
70 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
72 	} else if ((dev_priv->irq_mask_reg & mask) != 0) {
73 		dev_priv->irq_mask_reg &= ~mask;
74 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
81 igdng_disable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq)
83 	if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != mask)) {
84 		dev_priv->gt_irq_mask_reg |= mask;
85 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
87 	} else if ((dev_priv->irq_mask_reg & mask) != mask) {
88 		dev_priv->irq_mask_reg |= mask;
89 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
96 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
98        if ((dev_priv->irq_mask_reg & mask) != 0) {
99                dev_priv->irq_mask_reg &= ~mask;
100                I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
107 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
109        if ((dev_priv->irq_mask_reg & mask) != mask) {
110                dev_priv->irq_mask_reg |= mask;
111                I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
118 i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
120         if ((dev_priv->irq_mask_reg & mask) != 0) {
121                 dev_priv->irq_mask_reg &= ~mask;
122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
128 i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
130 	if ((dev_priv->irq_mask_reg & mask) != mask) {
131                 dev_priv->irq_mask_reg |= mask;
132                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
148 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, uint32_t mask)
150 	if ((dev_priv->pipestat[pipe] & mask) != mask) {
153 		dev_priv->pipestat[pipe] |= mask;
155 		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
161 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
163 	if ((dev_priv->pipestat[pipe] & mask) != 0) {
166 		dev_priv->pipestat[pipe] &= ~mask;
167 		I915_WRITE(reg, dev_priv->pipestat[pipe]);
184 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
195 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
238 	struct drm_i915_private *dev_priv = dev->dev_private;
241 	spin_lock_irqsave(&dev_priv->error_lock, flags);
243 	if (dev_priv->first_error)
273 	dev_priv->first_error = error;
291 	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
306 	struct drm_i915_private *dev_priv = dev->dev_private;
418        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
431        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
456         if (dev_priv->sarea_priv) {
457             dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
462                        dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
463                        DRM_WAKEUP(&dev_priv->irq_queue);
488         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
503 	if (dev_priv->sarea_priv) {
504 		if (dev_priv->hw_status_page)
505 	    		dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
517 		dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
518                 DRM_WAKEUP(&dev_priv->irq_queue);
526                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
543                 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
562 	drm_i915_private_t *dev_priv = dev->dev_private;
567 	dev_priv->counter++;
568 	if (dev_priv->counter > 0x7FFFFFFFUL)
569 		dev_priv->counter = 1;
570 	if (dev_priv->sarea_priv)
571 		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
578 		OUT_RING(dev_priv->counter);
581 		(void) READ_BREADCRUMB(dev_priv);
591 	OUT_RING(dev_priv->counter);
604 		(void) READ_BREADCRUMB(dev_priv);
609 		(void) READ_BREADCRUMB(dev_priv);
612 	return dev_priv->counter;
617 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
618 	spin_lock(&dev_priv->user_irq_lock);
619 	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
621                        igdng_enable_irq(dev_priv, GT_USER_INTERRUPT, 1);
623                        i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
625 	spin_unlock(&dev_priv->user_irq_lock);
631 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
632 	spin_lock(&dev_priv->user_irq_lock);
633 	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
635                        igdng_disable_irq(dev_priv, GT_USER_INTERRUPT, 1);
637                        i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
639 	spin_unlock(&dev_priv->user_irq_lock);
645 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
649 	if (!dev_priv) {
656 	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
657 		if (dev_priv->sarea_priv) {
658 			dev_priv->sarea_priv->last_dispatch =
659 				READ_BREADCRUMB(dev_priv);
663 	DRM_DEBUG("i915_wait_irq: irq_nr=%d breadcrumb=%d\n", irq_nr, READ_BREADCRUMB(dev_priv));
665 	DRM_WAIT_ON(ret, &dev_priv->irq_queue, 3 * DRM_HZ,
666 		    READ_BREADCRUMB(dev_priv) >= irq_nr);
673 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
679 	if (dev_priv->sarea_priv)
680 		dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
684 			DRM_DEBUG("EINTR wait %d now %d", dev_priv->counter, READ_BREADCRUMB(dev_priv));
700 	drm_i915_private_t *dev_priv = dev->dev_private;
706 	if (!dev_priv) {
741 	drm_i915_private_t *dev_priv = dev->dev_private;
744 	if (!dev_priv) {
757 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
765 	if ((dev_priv->de_irq_enable_reg & vblank) == 0) {
766 		igdng_enable_irq(dev_priv, vblank, 0);
767 		dev_priv->de_irq_enable_reg |= vblank;
768 		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
775 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
783 	if ((dev_priv->de_irq_enable_reg & vblank) != 0) {
784 		igdng_disable_irq(dev_priv, vblank, 0);
785 		dev_priv->de_irq_enable_reg &= ~vblank;
786 		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
793 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
801 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
805 		i915_enable_pipestat(dev_priv, pipe,
808 		i915_enable_pipestat(dev_priv, pipe,
810 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
817 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
819 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
823 	i915_disable_pipestat(dev_priv, pipe,
826 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
835 	drm_i915_private_t *dev_priv = dev->dev_private;
837 	if (!dev_priv) {
849 	drm_i915_private_t *dev_priv = dev->dev_private;
852 	if (!dev_priv) {
893        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
911        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
916        dev_priv->irq_mask_reg = ~display_mask;
917        dev_priv->de_irq_enable_reg = display_mask;
922        I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
923        I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
927        dev_priv->gt_irq_mask_reg = 0xffffffff;
928        dev_priv->gt_irq_enable_reg = render_mask;
932        I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
933        I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
941        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
955 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
957 	if (!dev_priv->mmio_map)
978 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
980 	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
984 		DRM_INIT_WAITQUEUE(&dev_priv->irq_queue, DRM_INTR_PRI(dev));
989 	dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
991 	dev_priv->pipestat[0] = 0;
992 	dev_priv->pipestat[1] = 0;
1018 	I915_WRITE(IMR, dev_priv->irq_mask_reg);
1022 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue, DRM_INTR_PRI(dev));
1029 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1030 	if ((!dev_priv) || (dev->irq_enabled == 0))
1033 	dev_priv->vblank_pipe = 0;
1037 		DRM_FINI_WAITQUEUE(&dev_priv->irq_queue);
1051 	DRM_FINI_WAITQUEUE(&dev_priv->irq_queue);