io/drm/i915_irq.c

70 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
74 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
85 		I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
89 		I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
100                I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
111                I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
122                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
132                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
155 		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
167 		I915_WRITE(reg, dev_priv->pipestat[pipe]);
332 			I915_WRITE(IPEIR_I965, ipeir);
340 			I915_WRITE(PGTBL_ER, pgtbl_err);
351 			I915_WRITE(PGTBL_ER, pgtbl_err);
379 			I915_WRITE(IPEIR, ipeir);
396 			I915_WRITE(IPEIR_I965, ipeir);
401 	I915_WRITE(EIR, eir);
410 		I915_WRITE(EMR, I915_READ(EMR) | eir);
411 		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
439 	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
451                I915_WRITE(DEIIR, de_iir);
453                I915_WRITE(GTIIR, gt_iir);
479 	I915_WRITE(DEIER, de_ier);
508 	I915_WRITE(IIR, iir);
536                 I915_WRITE(PIPEASTAT, pipea_stats);
553                 I915_WRITE(PIPEBSTAT, pipeb_stats);
768 		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
786 		I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
895        I915_WRITE(HWSTAM, 0xeffe);
899        I915_WRITE(DEIMR, 0xffffffff);
900        I915_WRITE(DEIER, 0x0);
904        I915_WRITE(GTIMR, 0xffffffff);
905        I915_WRITE(GTIER, 0x0);
920        I915_WRITE(DEIIR, I915_READ(DEIIR));
922        I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
923        I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
930        I915_WRITE(GTIIR, I915_READ(GTIIR));
932        I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
933        I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
942        I915_WRITE(HWSTAM, 0xffffffff);
944        I915_WRITE(DEIMR, 0xffffffff);
945        I915_WRITE(DEIER, 0x0);
946        I915_WRITE(DEIIR, I915_READ(DEIIR));
948        I915_WRITE(GTIMR, 0xffffffff);
949        I915_WRITE(GTIER, 0x0);
950        I915_WRITE(GTIIR, I915_READ(GTIIR));
966 	I915_WRITE(PIPEASTAT, 0);
967 	I915_WRITE(PIPEBSTAT, 0);
968 	I915_WRITE(IMR, 0xffffffff);
1007 	I915_WRITE(EMR, error_mask);
1010 	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1011 	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1015 	I915_WRITE(IIR, I915_READ(IIR));
1018 	I915_WRITE(IMR, dev_priv->irq_mask_reg);
1019 	I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
1041 	I915_WRITE(HWSTAM, 0xffffffff);
1042 	I915_WRITE(PIPEASTAT, 0);
1043 	I915_WRITE(PIPEBSTAT, 0);
1044 	I915_WRITE(IMR, 0xffffffff);
1045 	I915_WRITE(IER, 0x0);
1047 	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1048 	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1049 	I915_WRITE(IIR, I915_READ(IIR));