io/drm/i915_irq.c

58 /** Interrupts that we mask and unmask at runtime. */
66 igdng_enable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq)
68 	if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != 0)) {
69 		dev_priv->gt_irq_mask_reg &= ~mask;
72 	} else if ((dev_priv->irq_mask_reg & mask) != 0) {
73 		dev_priv->irq_mask_reg &= ~mask;
81 igdng_disable_irq(drm_i915_private_t *dev_priv, u32 mask, int gfx_irq)
83 	if (gfx_irq && ((dev_priv->gt_irq_mask_reg & mask) != mask)) {
84 		dev_priv->gt_irq_mask_reg |= mask;
87 	} else if ((dev_priv->irq_mask_reg & mask) != mask) {
88 		dev_priv->irq_mask_reg |= mask;
96 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
98        if ((dev_priv->irq_mask_reg & mask) != 0) {
99                dev_priv->irq_mask_reg &= ~mask;
107 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
109        if ((dev_priv->irq_mask_reg & mask) != mask) {
110                dev_priv->irq_mask_reg |= mask;
118 i915_enable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
120         if ((dev_priv->irq_mask_reg & mask) != 0) {
121                 dev_priv->irq_mask_reg &= ~mask;
128 i915_disable_irq(drm_i915_private_t *dev_priv, uint32_t mask)
130 	if ((dev_priv->irq_mask_reg & mask) != mask) {
131                 dev_priv->irq_mask_reg |= mask;
148 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, uint32_t mask)
150 	if ((dev_priv->pipestat[pipe] & mask) != mask) {
153 		dev_priv->pipestat[pipe] |= mask;
155 		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
161 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
163 	if ((dev_priv->pipestat[pipe] & mask) != 0) {
166 		dev_priv->pipestat[pipe] &= ~mask;
407 		 * mask them.
995 	 * Enable some error detection, note the instruction error mask