io/drm/i915_drv.c

187 vga_reg_put8(struct vgaregmap *regmap, uint16_t off, uint8_t val)
191 	ddi_put8(regmap->handle, regmap->addr + off, val);
198 vga_reg_get8(struct vgaregmap *regmap, uint16_t off)
203 	return (ddi_get8(regmap->handle, regmap->addr + off));
207 i915_write_indexed(struct vgaregmap *regmap,
210 	vga_reg_put8(regmap, index_port, index);
211 	vga_reg_put8(regmap, data_port, val);
215 i915_read_indexed(struct vgaregmap *regmap,
218 	vga_reg_put8(regmap, index_port, index);
219 	return (vga_reg_get8(regmap, data_port));
223 i915_write_ar(struct vgaregmap *regmap, uint16_t st01,
226 	(void) vga_reg_get8(regmap, st01);
227 	vga_reg_put8(regmap, VGA_AR_INDEX, palette_enable | reg);
228 	vga_reg_put8(regmap, VGA_AR_DATA_WRITE, val);
232 i915_read_ar(struct vgaregmap *regmap, uint16_t st01,
235 	(void) vga_reg_get8(regmap, st01);
236 	vga_reg_put8(regmap, VGA_AR_INDEX, index | palette_enable);
237 	return (vga_reg_get8(regmap, VGA_AR_DATA_READ));
298 	struct vgaregmap regmap;
300 	regmap.addr = (uint8_t *)s3_priv->saveAddr;
301 	regmap.handle = s3_priv->saveHandle;
304         s3_priv->saveDACMASK = vga_reg_get8(&regmap, VGA_DACMASK);
306 	vga_reg_put8(&regmap, VGA_DACRX, 0);
309 		s3_priv->saveDACDATA[i] = vga_reg_get8(&regmap, VGA_DACDATA);
312 	s3_priv->saveMSR = vga_reg_get8(&regmap, VGA_MSR_READ);
324 	i915_write_indexed(&regmap, cr_index, cr_data, 0x11,
325 	    i915_read_indexed(&regmap, cr_index, cr_data, 0x11) & (~0x80));
328 		    i915_read_indexed(&regmap, cr_index, cr_data, i);
333 	(void) vga_reg_get8(&regmap, st01);
334 	s3_priv->saveAR_INDEX = vga_reg_get8(&regmap, VGA_AR_INDEX);
336 		s3_priv->saveAR[i] = i915_read_ar(&regmap, st01, i, 0);
337 	(void) vga_reg_get8(&regmap, st01);
338 	vga_reg_put8(&regmap, VGA_AR_INDEX, s3_priv->saveAR_INDEX);
339 	(void) vga_reg_get8(&regmap, st01);
344 		    i915_read_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, i);
347 		i915_read_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
349 		i915_read_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
351 		i915_read_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
356 		    i915_read_indexed(&regmap, VGA_SR_INDEX, VGA_SR_DATA, i);
365 	struct vgaregmap regmap;
367 	regmap.addr = (uint8_t *)s3_priv->saveAddr;
368 	regmap.handle = s3_priv->saveHandle;
382 	vga_reg_put8(&regmap, VGA_MSR_WRITE, s3_priv->saveMSR);
396 		i915_write_indexed(&regmap, VGA_SR_INDEX, VGA_SR_DATA, i,
400 	i915_write_indexed(&regmap, cr_index, cr_data,
403 		i915_write_indexed(&regmap, cr_index,
408 		i915_write_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, i,
411 	i915_write_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
413 	i915_write_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
415 	i915_write_indexed(&regmap, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
419 	(void) vga_reg_get8(&regmap, st01); /* switch back to index mode */
421 	    i915_write_ar(&regmap, st01, i, s3_priv->saveAR[i], 0);
422 	(void) vga_reg_get8(&regmap, st01); /* switch back to index mode */
423 	vga_reg_put8(&regmap, VGA_AR_INDEX, s3_priv->saveAR_INDEX | 0x20);
424 	(void) vga_reg_get8(&regmap, st01); /* switch back to index mode */
427 	vga_reg_put8(&regmap, VGA_DACMASK, s3_priv->saveDACMASK);
429 	vga_reg_put8(&regmap, VGA_DACWX, 0);
432 		vga_reg_put8(&regmap, VGA_DACDATA, s3_priv->saveDACDATA[i]);