io/drm/i915_drv.c

289 		S3_WRITE(reg + (i << 2), array[i]);
550 	S3_WRITE(DSPARB, s3_priv->saveDSPARB);
557 		S3_WRITE(DPLL_A, s3_priv->saveDPLL_A &
561 	S3_WRITE(FPA0, s3_priv->saveFPA0);
562 	S3_WRITE(FPA1, s3_priv->saveFPA1);
564 	S3_WRITE(DPLL_A, s3_priv->saveDPLL_A);
567 		S3_WRITE(DPLL_A_MD, s3_priv->saveDPLL_A_MD);
571 	S3_WRITE(HTOTAL_A, s3_priv->saveHTOTAL_A);
572 	S3_WRITE(HBLANK_A, s3_priv->saveHBLANK_A);
573 	S3_WRITE(HSYNC_A, s3_priv->saveHSYNC_A);
574 	S3_WRITE(VTOTAL_A, s3_priv->saveVTOTAL_A);
575 	S3_WRITE(VBLANK_A, s3_priv->saveVBLANK_A);
576 	S3_WRITE(VSYNC_A, s3_priv->saveVSYNC_A);
577 	S3_WRITE(BCLRPAT_A, s3_priv->saveBCLRPAT_A);
580 	S3_WRITE(DSPASIZE, s3_priv->saveDSPASIZE);
581 	S3_WRITE(DSPAPOS, s3_priv->saveDSPAPOS);
582 	S3_WRITE(PIPEASRC, s3_priv->savePIPEASRC);
583 	S3_WRITE(DSPABASE, s3_priv->saveDSPABASE);
584 	S3_WRITE(DSPASTRIDE, s3_priv->saveDSPASTRIDE);
586 		S3_WRITE(DSPASURF, s3_priv->saveDSPASURF);
587 		S3_WRITE(DSPATILEOFF, s3_priv->saveDSPATILEOFF);
589 	S3_WRITE(PIPEACONF, s3_priv->savePIPEACONF);
592 	S3_WRITE(DSPACNTR, s3_priv->saveDSPACNTR);
593 	S3_WRITE(DSPABASE, S3_READ(DSPABASE));
597 		S3_WRITE(DPLL_B, s3_priv->saveDPLL_B &
601 	S3_WRITE(FPB0, s3_priv->saveFPB0);
602 	S3_WRITE(FPB1, s3_priv->saveFPB1);
604 	S3_WRITE(DPLL_B, s3_priv->saveDPLL_B);
607 		S3_WRITE(DPLL_B_MD, s3_priv->saveDPLL_B_MD);
611 	S3_WRITE(HTOTAL_B, s3_priv->saveHTOTAL_B);
612 	S3_WRITE(HBLANK_B, s3_priv->saveHBLANK_B);
613 	S3_WRITE(HSYNC_B, s3_priv->saveHSYNC_B);
614 	S3_WRITE(VTOTAL_B, s3_priv->saveVTOTAL_B);
615 	S3_WRITE(VBLANK_B, s3_priv->saveVBLANK_B);
616 	S3_WRITE(VSYNC_B, s3_priv->saveVSYNC_B);
617 	S3_WRITE(BCLRPAT_B, s3_priv->saveBCLRPAT_B);
620 	S3_WRITE(DSPBSIZE, s3_priv->saveDSPBSIZE);
621 	S3_WRITE(DSPBPOS, s3_priv->saveDSPBPOS);
622 	S3_WRITE(PIPEBSRC, s3_priv->savePIPEBSRC);
623 	S3_WRITE(DSPBBASE, s3_priv->saveDSPBBASE);
624 	S3_WRITE(DSPBSTRIDE, s3_priv->saveDSPBSTRIDE);
626 		S3_WRITE(DSPBSURF, s3_priv->saveDSPBSURF);
627 		S3_WRITE(DSPBTILEOFF, s3_priv->saveDSPBTILEOFF);
629 	S3_WRITE(PIPEBCONF, s3_priv->savePIPEBCONF);
632 	S3_WRITE(DSPBCNTR, s3_priv->saveDSPBCNTR);
633         S3_WRITE(DSPBBASE, S3_READ(DSPBBASE));
636 	S3_WRITE(ADPA, s3_priv->saveADPA);
640 		S3_WRITE(BLC_PWM_CTL2, s3_priv->saveBLC_PWM_CTL2);
642 		S3_WRITE(LVDS, s3_priv->saveLVDS);
644 		S3_WRITE(PFIT_CONTROL, s3_priv->savePFIT_CONTROL);
646 	S3_WRITE(PFIT_PGM_RATIOS, s3_priv->savePFIT_PGM_RATIOS);
647 	S3_WRITE(BLC_PWM_CTL, s3_priv->saveBLC_PWM_CTL);
648         S3_WRITE(LVDSPP_ON, s3_priv->saveLVDSPP_ON);
649         S3_WRITE(LVDSPP_OFF, s3_priv->saveLVDSPP_OFF);
650         S3_WRITE(PP_CYCLE, s3_priv->savePP_CYCLE);
651         S3_WRITE(PP_CONTROL, s3_priv->savePP_CONTROL);
656 	S3_WRITE(FBC_CFB_BASE, s3_priv->saveFBC_CFB_BASE);
657 	S3_WRITE(FBC_LL_BASE, s3_priv->saveFBC_LL_BASE);
658 	S3_WRITE(FBC_CONTROL2, s3_priv->saveFBC_CONTROL2);
659 	S3_WRITE(FBC_CONTROL, s3_priv->saveFBC_CONTROL);
662 	S3_WRITE(VGACNTRL, s3_priv->saveVGACNTRL);
663 	S3_WRITE(VCLK_DIVISOR_VGA0, s3_priv->saveVCLK_DIVISOR_VGA0);
664 	S3_WRITE(VCLK_DIVISOR_VGA1, s3_priv->saveVCLK_DIVISOR_VGA1);
665 	S3_WRITE(VCLK_POST_DIV, s3_priv->saveVCLK_POST_DIV);
689 		S3_WRITE(MCHBAR_RENDER_STANDBY, s3_priv->saveRENDERSTANDBY);
693 	S3_WRITE(HWS_PGA, s3_priv->saveHWS);
700 	S3_WRITE (D_STATE, s3_priv->saveD_STATE);
701 	S3_WRITE (CG_2D_DIS, s3_priv->saveCG_2D_DIS);
704 	S3_WRITE (CACHE_MODE_0, s3_priv->saveCACHE_MODE_0 | 0xffff0000);
707 	S3_WRITE (MI_ARB_STATE, s3_priv->saveMI_ARB_STATE | 0xffff0000);
710 		S3_WRITE(SWF0 + (i << 2), s3_priv->saveSWF0[i]);
711 		S3_WRITE(SWF10 + (i << 2), s3_priv->saveSWF1[i+7]);
714 		S3_WRITE(SWF30 + (i << 2), s3_priv->saveSWF2[i]);
716 	S3_WRITE(I915REG_PGTBL_CTRL, s3_priv->pgtbl_ctl);