io/drm/i915_dma.c

52 	drm_i915_private_t *dev_priv = dev->dev_private;
53 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
85        drm_i915_private_t *dev_priv = dev->dev_private;
96        dev_priv->status_page_dmah = dmah;
97        dev_priv->hw_status_page = (void *)dmah->vaddr;
98        dev_priv->dma_status_page = dmah->paddr;
100        (void) memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
102        I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
105        DRM_DEBUG("Enabled hardware status page add 0x%lx read GEM HWS 0x%x\n",dev_priv->hw_status_page, READ_HWSP(dev_priv, 0x20));
111        drm_i915_private_t *dev_priv = dev->dev_private;
113 		if (dev_priv->status_page_dmah) {
114 			DRM_DEBUG("free status_page_dmal %x", dev_priv->status_page_dmah);
115 			drm_pci_free(dev, dev_priv->status_page_dmah);
116 			dev_priv->status_page_dmah = NULL;
121 		if (dev_priv->status_gfx_addr) {
122 			DRM_DEBUG("free status_gfx_addr %x", dev_priv->status_gfx_addr);
123 			dev_priv->status_gfx_addr = 0;
124 			drm_core_ioremapfree(&dev_priv->hws_map, dev);
133 	drm_i915_private_t *dev_priv = dev->dev_private;
134 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
146 	drm_i915_private_t *dev_priv =
156 	if (dev_priv->ring.virtual_start) {
157 		drm_core_ioremapfree(&dev_priv->ring.map, dev);
158 		dev_priv->ring.virtual_start = 0;
159 		dev_priv->ring.map.handle = 0;
160 		dev_priv->ring.map.size = 0;
168 	dev_priv->sarea = NULL;
169 	dev_priv->sarea_priv = NULL;
177 	drm_i915_private_t *dev_priv =
181 	if (!dev_priv->sarea) {
183 		dev->dev_private = (void *)dev_priv;
188 	dev_priv->sarea_priv = (drm_i915_sarea_t *)(uintptr_t)
189 			((u8 *) dev_priv->sarea->handle +
193 		if (dev_priv->ring.ring_obj != NULL) {
200 		dev_priv->ring.Size = init->ring_size;
201 		dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
203 		dev_priv->ring.map.offset = (u_offset_t)init->ring_start;
204 		dev_priv->ring.map.size = init->ring_size;
205 		dev_priv->ring.map.type = 0;
206 		dev_priv->ring.map.flags = 0;
207 		dev_priv->ring.map.mtrr = 0;
209 		drm_core_ioremap(&dev_priv->ring.map, dev);
211 		if (dev_priv->ring.map.handle == NULL) {
219 	dev_priv->ring.virtual_start = (u8 *)dev_priv->ring.map.dev_addr;
220 	dev_priv->cpp = init->cpp;
221 	dev_priv->back_offset = init->back_offset;
222 	dev_priv->front_offset = init->front_offset;
223 	dev_priv->current_page = 0;
224 	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
228 	dev_priv->allow_batchbuffer = 1;
234 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
236 	if (!dev_priv->sarea) {
241 	if (dev_priv->ring.map.handle == NULL) {
248 	if (!dev_priv->hw_status_page) {
252 	DRM_DEBUG("i915_dma_resume hw status page @ %p\n", dev_priv->hw_status_page);
255 		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
257 		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
372 	drm_i915_private_t *dev_priv = dev->dev_private;
376 	if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) {
418 	drm_i915_private_t *dev_priv = dev->dev_private;
460 	drm_i915_private_t *dev_priv = dev->dev_private;
463 	dev_priv->counter++;
464 	if (dev_priv->counter > 0x7FFFFFFFUL)
465 		dev_priv->counter = 0;
466 	if (dev_priv->sarea_priv)
467 		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
473 	OUT_RING(dev_priv->counter);
514 	drm_i915_private_t *dev_priv = dev->dev_private;
564 	drm_i915_private_t *dev_priv = dev->dev_private;
567 	if (!dev_priv->sarea_priv)
571 		planes, dev_priv->sarea_priv->pf_current_page);
583 	if (dev_priv->current_page == 0) {
584 		OUT_RING(dev_priv->back_offset);
585 		dev_priv->current_page = 1;
587 		OUT_RING(dev_priv->front_offset);
588 		dev_priv->current_page = 0;
598 	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
603 	OUT_RING(dev_priv->counter);
607 	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
613 	drm_i915_private_t *dev_priv = dev->dev_private;
616 	ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
622 			   dev_priv->ring.head,
623 			   dev_priv->ring.tail,
624 			   dev_priv->ring.space);
648 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
650 	    dev_priv->sarea_priv;
654 	if (!dev_priv->allow_batchbuffer) {
677 		  batch.start, batch.used, batch.num_cliprects, dev_priv->counter);
692 	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
701 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
703 	    dev_priv->sarea_priv;
748 	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
775 	drm_i915_private_t *dev_priv = dev->dev_private;
779 	if (!dev_priv) {
802 		value = dev_priv->allow_batchbuffer ? 1 : 0;
805 		value = READ_BREADCRUMB(dev_priv);
829 	drm_i915_private_t *dev_priv = dev->dev_private;
832 	if (!dev_priv) {
844 		dev_priv->tex_lru_log_granularity = param.value;
847 		dev_priv->allow_batchbuffer = param.value;
861 	drm_i915_private_t *dev_priv = dev->dev_private;
867 	if (!dev_priv) {
875 	dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
876 	DRM_DEBUG("set gfx_addr 0x%08x\n", dev_priv->status_gfx_addr);
878 	dev_priv->hws_map.offset =
880 	dev_priv->hws_map.size = 4 * 1024; /* 4K pages */
881 	dev_priv->hws_map.type = 0;
882 	dev_priv->hws_map.flags = 0;
883 	dev_priv->hws_map.mtrr = 0;
886 	    dev_priv->hws_map.offset);
887 	drm_core_ioremap(&dev_priv->hws_map, dev);
888 	if (dev_priv->hws_map.handle == NULL) {
889 		dev->dev_private = (void *)dev_priv;
891 		dev_priv->status_gfx_addr = 0;
896 	dev_priv->hw_status_page = dev_priv->hws_map.dev_addr;
898 	(void) memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
899 	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
901 			dev_priv->status_gfx_addr);
902 	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
909 	struct drm_i915_private *dev_priv;
920 	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
921 	if (dev_priv == NULL)
924 	(void) memset(dev_priv, 0, sizeof(drm_i915_private_t));
925 	dev->dev_private = (void *)dev_priv;
926 	dev_priv->dev = dev;
932 	dev_priv->mmio_map = drm_alloc(sizeof (drm_local_map_t), DRM_MEM_MAPS);
933 	dev_priv->mmio_map->offset = base;
934 	dev_priv->mmio_map->size = size;
935 	dev_priv->mmio_map->type = _DRM_REGISTERS;
936 	dev_priv->mmio_map->flags = _DRM_REMOVABLE;
937 	(void) drm_ioremap(dev, dev_priv->mmio_map);
939 	DRM_DEBUG("i915_driverload mmio %p mmio_map->dev_addr %x", dev_priv->mmio_map, dev_priv->mmio_map->dev_addr);
974 	mutex_init(&dev_priv->user_irq_lock, "userirq", MUTEX_DRIVER, NULL);
975 	mutex_init(&dev_priv->error_lock, "error_lock", MUTEX_DRIVER, NULL);
988        drm_i915_private_t *dev_priv = dev->dev_private;
992 	drm_rmmap(dev, dev_priv->mmio_map);
994         mutex_destroy(&dev_priv->user_irq_lock);
1025 	drm_i915_private_t *dev_priv = dev->dev_private;
1027 	/* agp off can use this to get called before dev_priv */
1028 	if (!dev_priv)
1036 	if (dev_priv->agp_heap)
1037 		i915_mem_takedown(&(dev_priv->agp_heap));
1043 	drm_i915_private_t *dev_priv = dev->dev_private;
1044 	i915_mem_release(dev, fpriv, dev_priv->agp_heap);