Lines Matching refs:uintptr_t
204 dp->usd_lobase = (uintptr_t)base;
205 dp->usd_midbase = (uintptr_t)base >> 16;
206 dp->usd_hibase = (uintptr_t)base >> (16 + 8);
208 dp->usd_hilimit = (uintptr_t)size >> 16;
221 dp->usd_hilimit = (uintptr_t)size >> 16;
223 dp->usd_lobase = (uintptr_t)base;
224 dp->usd_midbase = (uintptr_t)base >> 16;
225 dp->usd_hibase = (uintptr_t)base >> (16 + 8);
247 dp->ssd_hilimit = (uintptr_t)size >> 16;
249 dp->ssd_lobase = (uintptr_t)base;
250 dp->ssd_midbase = (uintptr_t)base >> 16;
251 dp->ssd_hibase = (uintptr_t)base >> (16 + 8);
252 dp->ssd_hi64base = (uintptr_t)base >> (16 + 8 + 8);
265 uintptr_t base;
267 base = (uintptr_t)dp->ssd_lobase |
268 (uintptr_t)dp->ssd_midbase << 16 |
269 (uintptr_t)dp->ssd_hibase << (16 + 8) |
270 (uintptr_t)dp->ssd_hi64base << (16 + 8 + 8);
281 dp->ssd_hilimit = (uintptr_t)size >> 16;
283 dp->ssd_lobase = (uintptr_t)base;
284 dp->ssd_midbase = (uintptr_t)base >> 16;
285 dp->ssd_hibase = (uintptr_t)base >> (16 + 8);
297 uintptr_t base;
299 base = (uintptr_t)dp->ssd_lobase |
300 (uintptr_t)dp->ssd_midbase << 16 |
301 (uintptr_t)dp->ssd_hibase << (16 + 8);
318 dp->sgd_looffset = (uintptr_t)func;
319 dp->sgd_hioffset = (uintptr_t)func >> 16;
320 dp->sgd_hi64offset = (uintptr_t)func >> (16 + 16);
348 dp->sgd_looffset = (uintptr_t)func;
349 dp->sgd_hioffset = (uintptr_t)func >> 16;
394 ((uintptr_t)ldp & PAGEOFFSET);
608 kbm_read_only((uintptr_t)gdt0, gdtpa);
680 r_gdt.dtr_base = (uintptr_t)gdt0;
831 kbm_read_only((uintptr_t)gdt0, gdtpa);
884 r_gdt.dtr_base = (uintptr_t)gdt0;
1184 ASSERT(IS_P2ALIGNED((uintptr_t)gdt, PAGESIZE));
1252 ASSERT(IS_P2ALIGNED((uintptr_t)gdt, PAGESIZE));
1260 idtr.dtr_base = (uintptr_t)idt0;
1336 wrmsr(MSR_AMD_LSTAR, (uintptr_t)brand_sys_syscall);
1337 wrmsr(MSR_AMD_CSTAR, (uintptr_t)brand_sys_syscall32);
1344 wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)brand_sys_sysenter);
1380 wrmsr(MSR_AMD_LSTAR, (uintptr_t)sys_syscall);
1381 wrmsr(MSR_AMD_CSTAR, (uintptr_t)sys_syscall32);
1388 wrmsr(MSR_INTC_SEP_EIP, (uintptr_t)sys_sysenter);