i86pc/ml/locore.s

5  * Common Development and Distribution License (the "License").
11  * and limitations under the License.
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
23  * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
76  *	- The GDT and IDT are the callers; we need our copies.
77  *	- The kernel's text, initialized data and bss are mapped.
82  *	  and leave room for a phony "struct regs".
83  *	- Our GDT and IDT need to get munged.
120 	 * call back into boot - sysp (bootsvcs.h) and bootops (bootconf.h)
166 	 * and leave room for a "struct regs" for lwp0.  Note that the
185 	 * Save arguments and flags, if only for debugging ..
199 	 * Enable write protect and alignment check faults.
214 	 * main takes no args and should never return.
269 	 * and leave room for a phony "struct regs".
283 	 * Save all registers and flags
290 	 * Override bios settings and enable write protect and
296 	 * enable WP for detecting faults, and enable alignment checking.
300 	movl	%eax, %cr0		/ set the cr0 register correctly and
305 	 * and enabled.
322 	 * newer models from those vendors that support and do not disable
345 	 * assume the vendor is Cyrix and use the CCR's to enable cpuid
356 	 * even if the cpu vendor is Cyrix and the motherboard/chipset
358 	 * 0x21 corresponds with 0x23 and since 0x22 is still untouched,
359 	 * the reads and writes of 0x21 are guaranteed to be off-chip of
370 	 * read IMR and store in %bl
395 	 * if the ISR and the value read from 0x22 do not match then we have
419 	 * record the type and fix it later if not.
436 	 * have performed an external I/O cycle as well. In these cases and
452 	 * produced an external I/O cycle. In all known Cyrix models 6x86 and
453 	 * above, bit 3 of CCR3 is reserved and cannot be set to 1. In all
456 	 * 0xff. We test to see if I/O port 0x23 is pull-up or the IMR and
464 	 * DIR0 and DIR1. If we try to read DIR0, we may generate external I/O
465 	 * cycles, the exact behavior is model specific and undocumented.
468 	 * if bit 4 of CCR3 can be toggled, then DIR0 and DIR1 are supported.
503 	 * if bit 4 was not toggled DIR0 and DIR1 are not supported in which
530 	 * test for at least a 6x86, to see if we support both MAPEN and CPUID
582 	 * disable MAPEN and write CCR3
634 	 * early cyrix cpus are somewhat strange and need to be
677 	 * Processor signature and feature flags for Cyrix are insane.
679 	 * cautiously. Since we are Cyrix that has cpuid, we have DIR0 and DIR1
680 	 * Keep the family in %ebx and feature flags in %edx until not needed
695 	 * cpu's. We are pessimistic and when in doubt assume 6x86.
714 	 * although it is possible that we are a 6x86L, the cpu and
743 	 * registers and largely conform to the Pentium System Programming
745 	 * a crippled Pentium and hope for the best.
849 	 * maps to the values in DIR0 and DIR1. Just assume TSC is broken.
862 	 * We will be optimistic and hope that the chip is much like an MII,
863 	 * and that cpuid is sane. Cyrix seemed to have gotten it right in
886 	 * it when we see it. For now we just enable and test for MII features.
896  * cycles except page table accesses and interrupt ACK cycles do not assert
899  * prediction, register renaming, and execution of instructions down both the
900  * X and Y pipes for the xchgl instruction, short loops can be written that
911  * There is a group of undocumented registers on Cyrix 6x86, 6x86L, and
922  * fixed this bug sometime late in 1997 and no other exploits other than
934  	 * What is known about DBR1, DBR2, DBR3, and DOR is that for normal
935 	 * cpu execution DBR1, DBR2, and DBR3 are set to 0. To obtain opcode
936 	 * serialization, DBR1, DBR2, and DBR3 are loaded with 0xb8, 0x7f,
937 	 * and 0xff. Then, DOR is loaded with the one byte opcode.
947 	 * read CCR3 and mask out MAPEN
978 	 * disable MATCH and save in %bh
1078  *  When cmntrap gets called, the error code and trap number have been pushed.
1105 	 *   and contains the faulting address i.e. a copy of %cr2
1108 	 *   and contains the value of %db6
1111 	TRACE_PTR(%rdi, %rbx, %ebx, %rcx, $TT_TRAP) /* Uses labels 8 and 9 */
1118 	 * this requires a call to getpcstack() and may induce recursion if an
1201 	 *   and contains the faulting address i.e. a copy of %cr2
1204 	 *   and contains the value of %db6
1207 	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
1214 	 * this requires a call to getpcstack() and may induce recursion if an
1327 	TRACE_PTR(%rdi, %rbx, %ebx, %rcx, $TT_TRAP) /* Uses labels 8 and 9 */
1361 	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
1410 	TRACE_PTR(%rdi, %rbx, %ebx, %rcx, $TT_TRAP) /* Uses labels 8 and 9 */
1438 	TRACE_PTR(%edi, %ebx, %ebx, %ecx, $TT_TRAP) /* Uses labels 8 and 9 */
1536 	 * If agent lwp, clear %fs and %gs
1634          * If agent lwp, clear %fs and %gs.
1677 	 * There can be no instructions between this label and IRET or
1720  * horribly broken and can be used with some care, and those that have a
1737 	 * XX64 quick and dirty port from the i386 version. Since we
1749 / elapses between reads. A reliable TSC can be read as often and as rapidly
1750 / as desired. The simplistic approach of reading the TSC counter and
1753 / and then the TSC and PIT counter are correlated. In practice very rarely
1755 / taken to prevent the PIT counter from wrapping beyond its resolution and for
1764 / marginal TSC's and/or IO, if this value is too small on those, it may
1768 / will still work and the caller should be able to handle variances in the
1769 / calculation of cpu frequency, but the calculation will be inefficient and
1781 / The following block of code up to and including the latching of the PIT
1782 / counter after freq_tsc_perf_loop is very critical and very carefully
1792 	/ initialize the PIT counter and start a count down
1799 	/ read the TSC and store the TS in %edi:%esi
1809 	/ read the TSC and store the LSW in %ecx
1813 	/ latch the PIT counter and status
1952 / elapses between reads. A reliable TSC can be read as often and as rapidly
1953 / as desired. The simplistic approach of reading the TSC counter and
1956 / and then the TSC and PIT counter are correlated. In practice very rarely
1958 / taken to prevent the PIT counter from wrapping beyond its resolution and for
1967 / marginal TSC's and/or IO, if this value is too small on those, it may
1971 / will still work and the caller should be able to handle variances in the
1972 / calculation of cpu frequency, but the calculation will be inefficient and
1984 / The following block of code up to and including the latching of the PIT
1985 / counter after freq_tsc_perf_loop is very critical and very carefully
1995 	/ initialize the PIT counter and start a count down
2002 	/ read the TSC and store the TS in %edi:%esi
2012 	/ read the TSC and store the LSW in %ecx
2016 	/ latch the PIT counter and status
2186 	/ initialize the PIT counter and start a count down
2207 	/ latch the PIT counter and status