i86pc/io/immu_qinv.c

37 #include <sys/immu.h>
161 static void qinv_submit_inv_dsc(immu_t *immu, qinv_dsc_t *dsc);
162 static void qinv_context_common(immu_t *immu, uint8_t function_mask,
164 static void qinv_iotlb_common(immu_t *immu, uint_t domain_id,
166 static void qinv_iec_common(immu_t *immu, uint_t iidx,
169 static void qinv_wait_sync(immu_t *immu, immu_inv_wait_t *iwp);
171 static void qinv_dev_iotlb_common(immu_t *immu, uint16_t sid,
177 qinv_submit_inv_dsc(immu_t *immu, qinv_dsc_t *dsc)
186 	qinv = (qinv_t *)immu->immu_qinv;
205 		    immu_regs_get64(immu, IMMU_REG_INVAL_QH));
214 	immu_regs_put64(immu, IMMU_REG_INVAL_QT,
222 qinv_context_common(immu_t *immu, uint8_t function_mask,
230 	qinv_submit_inv_dsc(immu, &dsc);
235 qinv_iotlb_common(immu_t *immu, uint_t domain_id,
242 	if (IMMU_CAP_GET_DRD(immu->immu_regs_cap))
244 	if (IMMU_CAP_GET_DWD(immu->immu_regs_cap))
249 		if (!IMMU_CAP_GET_PSI(immu->immu_regs_cap) ||
250 		    am > IMMU_CAP_GET_MAMV(immu->immu_regs_cap) ||
274 	qinv_submit_inv_dsc(immu, &dsc);
279 qinv_dev_iotlb_common(immu_t *immu, uint16_t sid,
287 	qinv_submit_inv_dsc(immu, &dsc);
292 qinv_iec_common(immu_t *immu, uint_t iidx, uint_t im, uint_t g)
299 	qinv_submit_inv_dsc(immu, &dsc);
307 qinv_wait_sync(immu_t *immu, immu_inv_wait_t *iwp)
331 	qinv_submit_inv_dsc(immu, &dsc);
375 qinv_setup(immu_t *immu)
401 	mutex_init(&(immu->immu_qinv_lock), NULL, MUTEX_DRIVER, NULL);
404 	mutex_enter(&(immu->immu_qinv_lock));
406 	immu->immu_qinv = NULL;
407 	if (!IMMU_ECAP_GET_QI(immu->immu_regs_excap) ||
409 		mutex_exit(&(immu->immu_qinv_lock));
489 	immu->immu_qinv = qinv;
491 	mutex_exit(&(immu->immu_qinv_lock));
507 	mutex_exit(&(immu->immu_qinv_lock));
526 	immu_t *immu;
534 	immu = list_head(listp);
535 	for (; immu; immu = list_next(listp, immu)) {
536 		if (qinv_setup(immu) == DDI_SUCCESS) {
537 			immu->immu_qinv_setup = B_TRUE;
548 immu_qinv_startup(immu_t *immu)
553 	if (immu->immu_qinv_setup == B_FALSE) {
557 	qinv = (qinv_t *)immu->immu_qinv;
559 	immu_regs_qinv_enable(immu, qinv_reg_value);
560 	immu->immu_flushops = &immu_qinv_flushops;
561 	immu->immu_qinv_running = B_TRUE;
569 immu_qinv_context_fsi(immu_t *immu, uint8_t function_mask,
572 	qinv_context_common(immu, function_mask, source_id,
574 	qinv_wait_sync(immu, iwp);
582 immu_qinv_context_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
584 	qinv_context_common(immu, 0, 0, domain_id, CTT_INV_G_DOMAIN);
585 	qinv_wait_sync(immu, iwp);
593 immu_qinv_context_gbl(immu_t *immu, immu_inv_wait_t *iwp)
595 	qinv_context_common(immu, 0, 0, 0, CTT_INV_G_GLOBAL);
596 	qinv_wait_sync(immu, iwp);
604 immu_qinv_iotlb_psi(immu_t *immu, uint_t domain_id,
610 	max_am = IMMU_CAP_GET_MAMV(immu->immu_regs_cap);
613 	if (IMMU_CAP_GET_PSI(immu->immu_regs_cap)) {
617 				qinv_iotlb_common(immu, domain_id,
624 			qinv_iotlb_common(immu, domain_id,
630 		qinv_iotlb_common(immu, domain_id, dvma,
634 	qinv_wait_sync(immu, iwp);
642 immu_qinv_iotlb_dsi(immu_t *immu, uint_t domain_id, immu_inv_wait_t *iwp)
644 	qinv_iotlb_common(immu, domain_id, 0, 0, 0, TLB_INV_G_DOMAIN);
645 	qinv_wait_sync(immu, iwp);
653 immu_qinv_iotlb_gbl(immu_t *immu, immu_inv_wait_t *iwp)
655 	qinv_iotlb_common(immu, 0, 0, 0, 0, TLB_INV_G_GLOBAL);
656 	qinv_wait_sync(immu, iwp);
661 immu_qinv_intr_global(immu_t *immu, immu_inv_wait_t *iwp)
663 	qinv_iec_common(immu, 0, 0, IEC_INV_GLOBAL);
664 	qinv_wait_sync(immu, iwp);
669 immu_qinv_intr_one_cache(immu_t *immu, uint_t iidx, immu_inv_wait_t *iwp)
671 	qinv_iec_common(immu, iidx, 0, IEC_INV_INDEX);
672 	qinv_wait_sync(immu, iwp);
677 immu_qinv_intr_caches(immu_t *immu, uint_t iidx, uint_t cnt,
687 			qinv_iec_common(immu, iidx + cnt, 0, IEC_INV_INDEX);
689 		qinv_wait_sync(immu, iwp);
697 	if (mask > IMMU_ECAP_GET_MHMV(immu->immu_regs_excap)) {
699 			qinv_iec_common(immu, iidx + cnt, 0, IEC_INV_INDEX);
701 		qinv_wait_sync(immu, iwp);
705 	qinv_iec_common(immu, iidx, mask, IEC_INV_INDEX);
707 	qinv_wait_sync(immu, iwp);
711 immu_qinv_report_fault(immu_t *immu)
718 	mutex_enter(&(immu->immu_qinv_lock));
720 	qinv = (qinv_t *)(immu->immu_qinv);
723 	    immu_regs_get64(immu, IMMU_REG_INVAL_QH));
729 	ddi_err(DER_WARN, immu->immu_dip,
738 	mutex_exit(&(immu->immu_qinv_lock));