sys/nxge/nxge_rxdma_hw.h

41 #define	RX_DMA_CK_DIV_SHIFT	0			/* bits 15:0 */
62 	} bits;
74 #define	DEF_PT_RDC_SHIFT	0			/* bits 4:0 */
79 #define	RDC_TBL_SHIFT		0			/* bits 4:0 */
101 	} bits;
122 	} bits;
129 #define	RX_ADDR_MD_SHIFT	0			/* bits 0:0 */
155 	} bits;
168 #define	PT_DRR_WT_MASK		0x000000000000FFFFULL	/* bits 15:0 */
189 	} bits;
201 #define	PT_USE_SHIFT		0			/* bits 19:0 */
222 	} bits;
253 #define	LOG_PAGE_ADDR_SHIFT	12	/* bits[43:12] --> bits[31:0] */
258 #define	RED_RAN_INIT_SHIFT	0			/* bits 15:0 */
282 	} bits;
309 #define	RDC_RED_PARA1_RBR_SCL_SHIFT	0			/* bits 2:0 */
315 #define	RDC_RED_PARA_WIN_SHIFT		0			/* bits 3:0 */
317 #define	RDC_RED_PARA_THRE_SHIFT	4			/* bits 15:4 */
319 #define	RDC_RED_PARA_WIN_SYN_SHIFT	16			/* bits 19:16 */
321 #define	RDC_RED_PARA_THRE_SYN_SHIFT	20			/* bits 31:20 */
347 	} bits;
359 #define	RXDMA_CFIG1_MBADDR_H_SHIFT	0			/* bits 11:0 */
392 	} bits;
432 	} bits;
447 #define	RBR_CFIG_A_STADDR_SHIFT		6			/* bits 17:6 */
449 #define	RBR_CFIG_A_STADDR_BASE_SHIFT	18			/* bits 43:18 */
451 #define	RBR_CFIG_A_LEN_SHIFT		48			/* bits 63:48 */
494 	} bits;
552 	} bits;
578 	} bits;
607 	} bits;
631 	} bits;
655 	} bits;
770 	} bits;
966 /* the following are write 1 to clear bits */
1037 	} bits;
1063 	} bits;
1085 	} bits;
1107 	} bits;
1129 	} bits;
1194 	} bits;
1319 	} bits;
1340 	} bits;
1366 	} bits;
1386 	} bits;
1428 	} bits;
1463 	} bits;
1496 	} bits;
1527 	} bits;
1559 	} bits;
1586 	} bits;
1630 	} bits;
1650 	} bits;
1695 	} bits;
1710 	} bits;
1721 	} bits;
1740 	} bits;
1751 	} bits;
1764 	} bits;
1775 	} bits;
1786 	} bits;
1797 	} bits;
1810 	} bits;
1821 	} bits;
1834 	} bits;
1847 	} bits;
1858 	} bits;
1875 	} bits;