hal/xgehal/xgehal-fifo.c

24 #include "xgehal-fifo.h"
40 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
73 	if (fifo->config->alignment_size) {
74 	        status =__hal_fifo_dtr_align_alloc_map(fifo, txdp);
79 			      fifo->align_size,
88 	if (fifo->channel.dtr_init) {
89 		fifo->channel.dtr_init(fifo, (xge_hal_dtr_h)txdp, index,
90 			   fifo->channel.userdata, XGE_HAL_CHANNEL_OC_NORMAL);
110 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)userdata;
123 	if (fifo->config->alignment_size) {
125 			xge_os_dma_unmap(fifo->channel.pdev,
128 			       fifo->align_size,
135 			xge_os_dma_free(fifo->channel.pdev,
137 			      fifo->align_size,
154 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
159 	hldev = (xge_hal_device_t *)fifo->channel.devh;
160 	fifo->config = &hldev->config.fifo;
161 	queue = &fifo->config->queue[attr->post_qid];
164 	xge_os_spin_lock_init(&fifo->channel.reserve_lock, hldev->pdev);
166 	xge_os_spin_lock_init_irq(&fifo->channel.reserve_lock, hldev->irqh);
170                 fifo->post_lock_ptr = &hldev->xena_post_lock;
172 	        xge_os_spin_lock_init(&fifo->channel.post_lock, hldev->pdev);
173                 fifo->post_lock_ptr = &fifo->channel.post_lock;
177                 fifo->post_lock_ptr = &hldev->xena_post_lock;
179 	        xge_os_spin_lock_init_irq(&fifo->channel.post_lock,
181                 fifo->post_lock_ptr = &fifo->channel.post_lock;
185 	fifo->align_size =
186 		fifo->config->alignment_size * fifo->config->max_aligned_frags;
191 	fifo->hw_pair =
196 	fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_UTILZ;
198 		fifo->interrupt_type = XGE_HAL_TXD_INT_TYPE_PER_LIST;
200 	fifo->no_snoop_bits =
226 	fifo->priv_size = sizeof(xge_hal_fifo_txdl_priv_t) +
228 	fifo->priv_size = ((fifo->priv_size + __xge_os_cacheline_size -1) /
233 	fifo->txdl_size = fifo->config->max_frags * sizeof(xge_hal_fifo_txd_t);
234 	txdl_size = ((fifo->txdl_size + __xge_os_cacheline_size - 1) /
237 	if (fifo->txdl_size != txdl_size)
239 		fifo->config->max_frags, fifo->txdl_size, txdl_size,
242 	fifo->txdl_size = txdl_size;
247 	fifo->channel.dtr_init = attr->dtr_init;
248 	fifo->channel.userdata = attr->userdata;
249 	fifo->txdl_per_memblock = fifo->config->memblock_size /
250 		fifo->txdl_size;
252 	fifo->mempool = __hal_mempool_create(hldev->pdev,
253 					     fifo->config->memblock_size,
254 					     fifo->txdl_size,
255 					     fifo->priv_size,
260 					     fifo);
261 	if (fifo->mempool == NULL) {
266 					(void **) __hal_mempool_items_arr(fifo->mempool),
268 					fifo->config->reserve_threshold);
277 		fifo->channel.reserve_length, fifo->channel.reserve_top,
278 		fifo->config->max_frags, fifo->config->reserve_threshold,
279 		fifo->config->memblock_size, fifo->config->alignment_size,
280 		fifo->config->max_aligned_frags);
283 	for ( i = 0; i < fifo->channel.reserve_length; i++) {
285 		" handle:%p", i, fifo->channel.reserve_arr[i]);
289 	xge_assert(fifo->channel.reserve_length);
291 	max_arr_index	= fifo->channel.reserve_length - 1;
292 	max_arr_index	-=fifo->channel.reserve_top;
294 	mid_point = (fifo->channel.reserve_length - fifo->channel.reserve_top)/2;
296 		dtrh =	fifo->channel.reserve_arr[i];
297 		fifo->channel.reserve_arr[i] =
298 			fifo->channel.reserve_arr[max_arr_index - i];
299 		fifo->channel.reserve_arr[max_arr_index  - i] = dtrh;
303 	for ( i = 0; i < fifo->channel.reserve_length; i++) {
305 		" handle:%p", i, fifo->channel.reserve_arr[i]);
315 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
316 	xge_hal_device_t *hldev = (xge_hal_device_t *)fifo->channel.devh;
318 	if (fifo->mempool) {
319 		__hal_mempool_destroy(fifo->mempool);
325 	xge_os_spin_lock_destroy(&fifo->channel.reserve_lock, hldev->pdev);
327 	xge_os_spin_lock_destroy_irq(&fifo->channel.reserve_lock, hldev->pdev);
331 		xge_os_spin_lock_destroy(&fifo->channel.post_lock, hldev->pdev);
333 		xge_os_spin_lock_destroy_irq(&fifo->channel.post_lock,
398 		if (hldev->config.fifo.queue[i].configured) {
399 			int priority = hldev->config.fifo.queue[i].priority;
401 			    vBIT((hldev->config.fifo.queue[i].max-1),
418 					"fifo partition_%d at: "
434 	xge_debug_fifo(XGE_TRACE, "fifo partition_0 at: "
463 		if (!hldev->config.fifo.queue[i].configured ||
464 		    !hldev->config.fifo.queue[i].intr_vector)
481 				hldev->config.fifo.queue[i].intr_vector);
485 	xge_debug_fifo(XGE_TRACE, "%s", "fifo channels initialized");
494 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
499 		xge_os_dma_unmap(fifo->channel.pdev,
502 		       fifo->align_size,
509 	        xge_os_dma_free(fifo->channel.pdev,
511 	              fifo->align_size,
525 	xge_hal_fifo_t *fifo = (xge_hal_fifo_t *)channelh;
532 	txdl_priv->align_vaddr = (char *)xge_os_dma_malloc(fifo->channel.pdev,
533 				fifo->align_size,
543 	txdl_priv->align_dma_addr = xge_os_dma_map(fifo->channel.pdev,
545 		fifo->align_size,