Lines Matching refs:host

32   overheads used for both full and high speed host controller drivers. This
44 host controllers and also to high speed hub Transaction Translators (TT),
98 2.Host delay will be specific to particular hardware. The following host
99 delay is for RIO USB OHCI host controller (Provided by Ken Ward - RIO
101 "host delay" for given USB host controller implementation.
166 for the OHCI host controller.
168 - The host controller processes one interrupt endpoint descriptor list every
172 means each list is revisited once every 32ms. The host controller driver
180 - The host controller driver maintains an array of 32 frame bandwidth lists
188 The OHCI host controller driver will go through the following steps to
315 and isochronous endpoints. This will tell the host controller which micro-
350 isochronous endpoints. It will tell the host controller which micro frame
370 details for the EHCI host controller.
372 - The high speed host controller can support 256, 512 or 1024 periodic frame
373 lists. By default all host controllers will support 1024 frame lists. In
378 - The host controller traverses the periodic schedule by constructing an
383 - The host controller processes one interrupt endpoint descriptor list every
386 - The host controller driver sets up the interrupt lists to visit any given
403 TT acts as a full speed host controller & its bandwidth allocation scheme
405 speed host controller. Refer to the "Full speed bus" section for more
408 - The EHCI host controller driver maintains an array of 32 frame lists to
419 For a given high speed interrupt or isochronous endpoint, the EHCI host