Lines Matching defs:nvc
106 static int nv_add_legacy_intrs(nv_ctl_t *nvc);
108 static int nv_add_msi_intrs(nv_ctl_t *nvc);
110 static void nv_rem_intrs(nv_ctl_t *nvc);
122 static void nv_uninit_ctl(nv_ctl_t *nvc);
123 static void mcp5x_reg_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle);
124 static void ck804_reg_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle);
127 static int nv_init_ctl(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle);
128 static int mcp5x_packet_complete_intr(nv_ctl_t *nvc, nv_port_t *nvp);
130 static int mcp5x_dma_setup_intr(nv_ctl_t *nvc, nv_port_t *nvp);
135 static void nv_common_reg_init(nv_ctl_t *nvc);
136 static void ck804_intr_process(nv_ctl_t *nvc, uint8_t intr_status);
141 static void nv_cmn_err(int ce, nv_ctl_t *nvc, nv_port_t *nvp, char *fmt, ...);
164 static void nv_log(nv_ctl_t *nvc, nv_port_t *nvp, const char *fmt, ...);
172 static void nv_sgp_led_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle);
175 static int nv_sgp_init(nv_ctl_t *nvc);
176 static int nv_sgp_check_set_cmn(nv_ctl_t *nvc);
177 static int nv_sgp_csr_read(nv_ctl_t *nvc);
178 static void nv_sgp_csr_write(nv_ctl_t *nvc, uint32_t val);
179 static int nv_sgp_write_data(nv_ctl_t *nvc);
181 static void nv_sgp_drive_connect(nv_ctl_t *nvc, int drive);
182 static void nv_sgp_drive_disconnect(nv_ctl_t *nvc, int drive);
183 static void nv_sgp_drive_active(nv_ctl_t *nvc, int drive);
184 static void nv_sgp_locate(nv_ctl_t *nvc, int drive, int value);
185 static void nv_sgp_error(nv_ctl_t *nvc, int drive, int value);
186 static void nv_sgp_cleanup(nv_ctl_t *nvc);
573 nv_ctl_t *nvc;
593 nvc = ddi_get_soft_state(nv_statep, inst);
595 nvc->nvc_dip = dip;
597 NVLOG(NVDBG_INIT, nvc, NULL, "nv_attach(): DDI_ATTACH", NULL);
602 nvc->nvc_revid = pci_config_get8(pci_conf_handle,
604 NVLOG(NVDBG_INIT, nvc, NULL,
606 inst, nvc->nvc_revid, nv_debug_flags);
640 (caddr_t *)&nvc->nvc_bar_addr[bar], 0, 0, &accattr,
641 &nvc->nvc_bar_hdl[bar]);
644 NVLOG(NVDBG_INIT, nvc, NULL,
656 status = nv_init_ctl(nvc, pci_conf_handle);
659 NVLOG(NVDBG_INIT, nvc, NULL, "nv_init_ctl failed",
670 mutex_init(&nvc->nvc_mutex, NULL, MUTEX_DRIVER,
671 DDI_INTR_PRI(nvc->nvc_intr_pri));
680 nv_cmn_err(CE_WARN, nvc, NULL,
686 NVLOG(NVDBG_INIT, nvc, NULL,
692 NVLOG(NVDBG_INIT, nvc, NULL,
699 if (nv_add_msi_intrs(nvc) == DDI_SUCCESS) {
700 nvc->nvc_intr_type = DDI_INTR_TYPE_MSI;
702 NVLOG(NVDBG_INIT, nvc, NULL,
705 nv_cmn_err(CE_CONT, nvc, NULL,
719 NVLOG(NVDBG_INIT, nvc, NULL,
722 if (nv_add_legacy_intrs(nvc) == DDI_SUCCESS) {
723 nvc->nvc_intr_type = DDI_INTR_TYPE_FIXED;
725 NVLOG(NVDBG_INIT, nvc, NULL,
728 nv_cmn_err(CE_WARN, nvc, NULL,
730 NVLOG(NVDBG_INIT, nvc, NULL,
737 NVLOG(NVDBG_INIT, nvc, NULL,
748 nvc->nvc_ctlr_num = PCI_REG_FUNC_G(regs->pci_phys_hi);
754 nv_sgp_led_init(nvc, pci_conf_handle);
765 nvp = &(nvc->nvc_port[j]);
789 if (sata_hba_attach(nvc->nvc_dip,
790 &nvc->nvc_sata_hba_tran,
799 NVLOG(NVDBG_INIT, nvc, NULL, "nv_attach DDI_SUCCESS", NULL);
805 nvc = ddi_get_soft_state(nv_statep, inst);
807 NVLOG(NVDBG_INIT, nvc, NULL,
832 nvc->nvc_state &= ~NV_CTRL_SUSPEND;
834 for (i = 0; i < NV_MAX_PORTS(nvc); i++) {
835 nv_resume(&(nvc->nvc_port[i]));
852 nv_rem_intrs(nvc);
862 for (; port < NV_MAX_PORTS(nvc); port++) {
863 nvp = &(nvc->nvc_port[port]);
871 mutex_destroy(&nvc->nvc_mutex);
875 nv_uninit_ctl(nvc);
880 ddi_regs_map_free(&nvc->nvc_bar_hdl[bar]);
902 nv_ctl_t *nvc;
905 nvc = ddi_get_soft_state(nv_statep, inst);
911 NVLOG(NVDBG_INIT, nvc, NULL, "nv_detach: DDI_DETACH", NULL);
916 nv_rem_intrs(nvc);
921 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
922 nvp = &(nvc->nvc_port[port]);
932 ddi_regs_map_free(&nvc->nvc_bar_hdl[i]);
938 mutex_destroy(&nvc->nvc_mutex);
943 nv_uninit_ctl(nvc);
949 nv_sgp_cleanup(nvc);
955 (void) sata_hba_detach(nvc->nvc_dip, DDI_DETACH);
966 NVLOG(NVDBG_INIT, nvc, NULL, "nv_detach: DDI_SUSPEND", NULL);
968 for (i = 0; i < NV_MAX_PORTS(nvc); i++) {
969 nv_suspend(&(nvc->nvc_port[i]));
972 nvc->nvc_state |= NV_CTRL_SUSPEND;
986 nv_ctl_t *nvc;
995 nvc = ddi_get_soft_state(nv_statep, instance);
996 if (nvc != NULL) {
997 *result = nvc->nvc_dip;
1018 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, getminor(*devp));
1020 if (nvc == NULL) {
1040 nv_ctl_t *nvc;
1053 nvc = ddi_get_soft_state(nv_statep, inst);
1054 if (nvc == NULL) {
1058 if ((nvc->nvc_sgp_cbp == NULL) || (nvc->nvc_sgp_cmn == NULL)) {
1091 nv_sgp_error(nvc, drive, TR_ERROR_DISABLE);
1093 nv_sgp_locate(nvc, drive, TR_LOCATE_DISABLE);
1099 nvc->nvc_port[port].nvp_sgp_ioctl_mod |= led.led_type;
1104 nv_sgp_error(nvc, drive, TR_ERROR_ENABLE);
1106 nv_sgp_locate(nvc, drive, TR_LOCATE_ENABLE);
1112 nvc->nvc_port[port].nvp_sgp_ioctl_mod |= led.led_type;
1134 curr_led = SGPIO0_TR_DRV(nvc->nvc_sgp_cbp->sgpio0_tr,
1138 if (nvc->nvc_port[port].nvp_sgp_ioctl_mod & led.led_type) {
1205 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1213 if (cport >= NV_MAX_PORTS(nvc)) {
1220 ASSERT(nvc->nvc_port != NULL);
1221 nvp = &(nvc->nvc_port[cport]);
1224 NVLOG(NVDBG_ENTRY, nvc, nvp,
1235 nv_cmn_err(CE_WARN, nvc, nvp,
1258 nv_cmn_err(CE_WARN, nvc, nvp,
1329 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1330 nv_port_t *nvp = &(nvc->nvc_port[cport]);
1333 NVLOG(NVDBG_ENTRY, nvc, nvp, "nv_sata_start: opmode: 0x%x cmd=%x",
1340 NVLOG(NVDBG_ERRS, nvc, nvp,
1353 NVLOG(NVDBG_ERRS, nvc, nvp,
1366 NVLOG(NVDBG_ERRS, nvc, nvp,
1378 NVLOG(NVDBG_ERRS, nvc, nvp,
1392 NVLOG(NVDBG_ERRS, nvc, nvp,
1399 NVLOG(NVDBG_ERRS, nvc, nvp,
1415 NVLOG(NVDBG_ERRS, nvc, nvp,
1428 nv_cmn_err(CE_WARN, nvc, nvp,
1446 NVLOG(NVDBG_RESET, nvc, nvp,
1467 NVLOG(NVDBG_RESET, nvc, nvp,
1480 NVLOG(NVDBG_ERRS, nvc, nvp,
1540 nv_ctl_t *nvc = nvp->nvp_ctlp;
1574 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE);
1585 (*(nvc->nvc_set_intr))(nvp, NV_INTR_ENABLE);
1596 (*(nvc->nvc_set_intr))(nvp, NV_INTR_ENABLE);
1624 nv_ctl_t *nvc = nvp->nvp_ctlp;
1629 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait: enter", NULL);
1635 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait: before nv_wait",
1645 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait: "
1651 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait: before nvc_intr",
1657 ret = (*(nvc->nvc_interrupt))((caddr_t)nvc, NULL);
1658 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait: after nvc_intr",
1662 NVLOG(NVDBG_SYNC, nvc, nvp, "nv_poll_wait:"
1695 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1696 nv_port_t *nvp = &(nvc->nvc_port[cport]);
1699 ASSERT(cport < NV_MAX_PORTS(nvc));
1700 NVLOG(NVDBG_ENTRY, nvc, nvp, "nv_sata_abort %d %p", flag, spkt);
1706 nv_cmn_err(CE_WARN, nvc, nvp,
1718 NVLOG(NVDBG_ENTRY, nvc, nvp,
1723 NVLOG(NVDBG_ENTRY, nvc, nvp, "no spkts to abort", NULL);
1725 NVLOG(NVDBG_ENTRY, nvc, nvp,
1815 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1816 nv_port_t *nvp = &(nvc->nvc_port[cport]);
1819 ASSERT(cport < NV_MAX_PORTS(nvc));
1821 NVLOG(NVDBG_ENTRY, nvc, nvp, "nv_sata_reset", NULL);
1838 NVLOG(NVDBG_RESET, nvc, nvp,
1850 NVLOG(NVDBG_RESET, nvc, nvp, "in_panic. nvp_state: "
1900 NVLOG(NVDBG_ENTRY, nvc, nvp,
1906 NVLOG(NVDBG_ENTRY, nvc, nvp,
1929 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1930 nv_port_t *nvp = &(nvc->nvc_port[cport]);
1934 ASSERT(cport < NV_MAX_PORTS(nvc));
1935 NVLOG(NVDBG_ENTRY, nvc, nvp, "nv_sata_activate", NULL);
1943 (*(nvc->nvc_set_intr))(nvp, NV_INTR_ENABLE);
1983 nv_ctl_t *nvc = ddi_get_soft_state(nv_statep, ddi_get_instance(dip));
1984 nv_port_t *nvp = &(nvc->nvc_port[cport]);
1986 ASSERT(cport < NV_MAX_PORTS(nvc));
1987 NVLOG(NVDBG_ENTRY, nvc, nvp, "nv_sata_deactivate", NULL);
2001 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE);
2023 nv_ctl_t *nvc = nvp->nvp_ctlp;
2027 NVLOG(NVDBG_DELIVER, nvc, nvp, "nv_start_common entered: cmd: 0x%x",
2051 sactive = nv_get32(nvc->nvc_bar_hdl[5],
2054 nv_put32(nvc->nvc_bar_hdl[5], nvp->nvp_sactive, on_bit);
2055 NVLOG(NVDBG_DELIVER, nvc, nvp, "setting SACTIVE onbit: %X",
2096 NVLOG(NVDBG_DELIVER, nvc, nvp, "DMA command", NULL);
2100 NVLOG(NVDBG_DELIVER, nvc, nvp, "packet command", NULL);
2119 NVLOG(NVDBG_DELIVER, nvc, nvp, "non-data command", NULL);
2123 NVLOG(NVDBG_DELIVER, nvc, nvp, "pio in command", NULL);
2139 NVLOG(NVDBG_DELIVER, nvc, nvp, "pio out command", NULL);
2147 nv_cmn_err(CE_WARN, nvc, nvp, "malformed command: direction"
2337 nv_ctl_t *nvc = nvp->nvp_ctlp;
2374 NVLOG(NVDBG_RESET, nvc, nvp, "npv_reset_retry_count: %d",
2382 NVLOG(NVDBG_RESET, nvc, nvp, "nvp_reset_count: %d reason: %s "
2398 nv_cmn_err(CE_NOTE, nvc, nvp, "nv_reset: reason: %s serr 0x%x"
2452 NVLOG(NVDBG_RESET, nvc, nvp, "nv_reset: applied (%d); "
2483 NVLOG(NVDBG_RESET, nvc, nvp, "nv_reset not succeeded "
2486 NVLOG(NVDBG_RESET, nvc, nvp, "nv_reset succeeded"
2501 mcp5x_reg_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle)
2504 uchar_t *bar5 = nvc->nvc_bar_addr[5];
2507 nvc->nvc_mcp5x_ctl = (uint32_t *)(bar5 + MCP5X_CTL);
2508 nvc->nvc_mcp5x_ncq = (uint32_t *)(bar5 + MCP5X_NCQ);
2510 for (port = 0, off = 0; port < NV_MAX_PORTS(nvc); port++, off += 2) {
2511 nvp = &(nvc->nvc_port[port]);
2520 nv_put16(nvc->nvc_bar_hdl[5], nvp->nvp_mcp5x_int_status,
2532 nv_put16(nvc->nvc_bar_hdl[5], nvp->nvp_mcp5x_int_ctl,
2542 nv_put32(nvc->nvc_bar_hdl[5], nvc->nvc_mcp5x_ncq, flags);
2544 nv_put32(nvc->nvc_bar_hdl[5], nvc->nvc_mcp5x_ctl, flags);
2552 if (nvc->nvc_revid >= 0xa3) {
2557 " enabled", nvc->nvc_revid);
2558 nvc->dma_40bit = B_TRUE;
2583 "not capable of 40-bit DMA addressing", nvc->nvc_revid);
2592 ck804_reg_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle)
2594 uchar_t *bar5 = nvc->nvc_bar_addr[5];
2610 reg16 = nv_get16(nvc->nvc_bar_hdl[5],
2612 nv_put16(nvc->nvc_bar_hdl[5], (uint16_t *)(bar5 + NV_ADMACTL_X),
2616 reg16 = nv_get16(nvc->nvc_bar_hdl[5],
2618 nv_put16(nvc->nvc_bar_hdl[5], (uint16_t *)(bar5 + NV_ADMACTL_Y),
2621 nvc->nvc_ck804_int_status = (uint8_t *)(bar5 + CK804_SATA_INT_STATUS);
2626 for (j = 0; j < NV_MAX_PORTS(nvc); j++) {
2627 nvp = &(nvc->nvc_port[j]);
2641 nv_init_ctl(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle)
2647 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
2648 uchar_t *bar5 = nvc->nvc_bar_addr[5];
2652 NVLOG(NVDBG_INIT, nvc, NULL, "nv_init_ctl entered", NULL);
2656 nvc->nvc_mcp5x_flag = B_FALSE;
2689 nvc->nvc_mcp5x_flag = B_TRUE;
2697 NVLOG(NVDBG_INIT, nvc, NULL, "controller is CK804", NULL);
2698 nvc->nvc_interrupt = ck804_intr;
2699 nvc->nvc_reg_init = ck804_reg_init;
2700 nvc->nvc_set_intr = ck804_set_intr;
2702 NVLOG(NVDBG_INIT, nvc, NULL, "controller is MCP51/MCP55", NULL);
2703 nvc->nvc_interrupt = mcp5x_intr;
2704 nvc->nvc_reg_init = mcp5x_reg_init;
2705 nvc->nvc_set_intr = mcp5x_set_intr;
2710 stran.sata_tran_hba_dip = nvc->nvc_dip;
2723 nvc->nvc_sata_hba_tran = stran;
2725 nvc->nvc_port = kmem_zalloc(sizeof (nv_port_t) * NV_MAX_PORTS(nvc),
2731 nv_common_reg_init(nvc);
2733 for (j = 0; j < NV_MAX_PORTS(nvc); j++) {
2734 nvp = &(nvc->nvc_port[j]);
2741 DDI_INTR_PRI(nvc->nvc_intr_pri));
2775 (*(nvc->nvc_reg_init))(nvc, pci_conf_handle);
2778 if (nvc->dma_40bit == B_TRUE)
2779 nvc->nvc_sata_hba_tran.sata_tran_hba_dma_attr =
2782 nvc->nvc_sata_hba_tran.sata_tran_hba_dma_attr =
2802 nv_ctl_t *nvc = nvp->nvp_ctlp;
2804 dev_info_t *dip = nvc->nvc_dip;
2946 nv_common_reg_init(nv_ctl_t *nvc)
2948 uchar_t *bar5_addr = nvc->nvc_bar_addr[5];
2953 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
2964 nvp = &(nvc->nvc_port[port]);
2965 nvp->nvp_ctlp = nvc;
2967 NVLOG(NVDBG_INIT, nvc, nvp, "setting up port mappings", NULL);
2969 nvp->nvp_cmd_hdl = nvc->nvc_bar_hdl[bar];
2970 nvp->nvp_cmd_addr = nvc->nvc_bar_addr[bar];
2971 nvp->nvp_ctl_hdl = nvc->nvc_bar_hdl[bar + 1];
2972 nvp->nvp_ctl_addr = nvc->nvc_bar_addr[bar + 1];
2973 nvp->nvp_bm_hdl = nvc->nvc_bar_hdl[NV_BAR_4];
2974 nvp->nvp_bm_addr = nvc->nvc_bar_addr[NV_BAR_4] +
2986 nv_uninit_ctl(nv_ctl_t *nvc)
2991 NVLOG(NVDBG_INIT, nvc, NULL, "nv_uninit_ctl entered", NULL);
2993 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
2994 nvp = &(nvc->nvc_port[port]);
2996 NVLOG(NVDBG_INIT, nvc, nvp, "uninitializing port", NULL);
3004 kmem_free(nvc->nvc_port, NV_MAX_PORTS(nvc) * sizeof (nv_port_t));
3005 nvc->nvc_port = NULL;
3017 nv_ctl_t *nvc = (nv_ctl_t *)arg1;
3019 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
3021 if (nvc->nvc_state & NV_CTRL_SUSPEND)
3024 intr_status = ddi_get8(bar5_hdl, nvc->nvc_ck804_int_status);
3031 ck804_intr_process(nvc, intr_status);
3043 ck804_intr_process(nv_ctl_t *nvc, uint8_t intr_status)
3054 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
3063 NVLOG(NVDBG_INTR, nvc, NULL,
3070 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
3079 NVLOG(NVDBG_INTR, nvc, NULL,
3082 nvp = &(nvc->nvc_port[port]);
3095 nv_put8(bar5_hdl, nvc->nvc_ck804_int_status,
3106 NVLOG(NVDBG_ALWAYS, nvc, nvp, "spurious interrupt "
3113 nv_put8(bar5_hdl, nvc->nvc_ck804_int_status,
3167 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
3170 nvp = &(nvc->nvc_port[port]);
3175 NVLOG(NVDBG_HOT, nvc, nvp,
3194 ASSERT(nvc->nvc_port[port].nvp_sstatus);
3197 nvc->nvc_port[port].nvp_sstatus);
3210 nv_put8(bar5_hdl, nvc->nvc_ck804_int_status, clear_bits);
3217 intr_status = nv_get8(bar5_hdl, nvc->nvc_ck804_int_status);
3223 NVLOG(NVDBG_ALWAYS, nvc, nvp, "inst_status=%x "
3226 nv_put8(bar5_hdl, nvc->nvc_ck804_int_status,
3229 nvc->nvc_ck804_int_status);
3238 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE);
3244 nv_cmn_err(CE_WARN, nvc, nvp, "unable to clear "
3261 nv_ctl_t *nvc = nvp->nvp_ctlp;
3262 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
3271 NVLOG(NVDBG_INTR, nvc, nvp, "mcp55_intr_port entered", NULL);
3291 NVLOG(NVDBG_INTR, nvc, nvp, "int_status = %x", int_status);
3313 NVLOG(NVDBG_INTR, nvc, nvp,
3324 if (mcp5x_packet_complete_intr(nvc, nvp) ==
3333 NVLOG(NVDBG_INTR, nvc, nvp, "mcp5x_dma_setup_intr",
3343 ret = mcp5x_dma_setup_intr(nvc, nvp);
3373 NVLOG(NVDBG_INTR, nvc, nvp, "excessive interrupt "
3379 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE);
3415 NVLOG(NVDBG_INTR, nvc, nvp, "mcp55_intr_port: finished ret=%d", ret);
3433 nv_ctl_t *nvc = (nv_ctl_t *)arg1;
3436 if (nvc->nvc_state & NV_CTRL_SUSPEND)
3439 ret = mcp5x_intr_port(&(nvc->nvc_port[0]));
3440 ret |= mcp5x_intr_port(&(nvc->nvc_port[1]));
3461 mcp5x_dma_setup_intr(nv_ctl_t *nvc, nv_port_t *nvp)
3470 nv_cmn_err(CE_PANIC, nvc, nvp,
3475 slot = nv_get32(nvc->nvc_bar_hdl[5], nvc->nvc_mcp5x_ncq);
3479 NVLOG(NVDBG_INTR, nvc, nvp, "mcp5x_dma_setup_intr slot %d"
3491 NVLOG(NVDBG_INTR, nvc, nvp, "BM was already enabled for "
3511 mcp5x_packet_complete_intr(nv_ctl_t *nvc, nv_port_t *nvp)
3526 NVLOG(NVDBG_INTR, nvc, nvp, "BMISX_IDEINTS not set %x",
3547 nv_cmn_err(CE_WARN, nvc, nvp,
3595 sactive = nv_get32(nvc->nvc_bar_hdl[5], nvp->nvp_sactive);
3609 nv_cmn_err(CE_CONT, nvc, nvp, "ERROR sactive = %X "
3775 nv_add_legacy_intrs(nv_ctl_t *nvc)
3777 dev_info_t *devinfo = nvc->nvc_dip;
3781 NVLOG(NVDBG_INIT, nvc, NULL, "nv_add_legacy_intrs", NULL);
3788 NVLOG(NVDBG_INIT, nvc, NULL,
3798 nvc->nvc_intr_size = count * sizeof (ddi_intr_handle_t);
3799 nvc->nvc_htable = kmem_zalloc(nvc->nvc_intr_size, KM_SLEEP);
3804 rc = ddi_intr_alloc(devinfo, nvc->nvc_htable, DDI_INTR_TYPE_FIXED,
3808 nv_cmn_err(CE_WARN, nvc, NULL,
3810 kmem_free(nvc->nvc_htable, nvc->nvc_intr_size);
3816 nv_cmn_err(CE_WARN, nvc, NULL,
3823 nvc->nvc_intr_cnt = actual;
3828 if (ddi_intr_get_pri(nvc->nvc_htable[0], &nvc->nvc_intr_pri) !=
3830 nv_cmn_err(CE_WARN, nvc, NULL, "ddi_intr_get_pri() failed");
3838 if (nvc->nvc_intr_pri >= ddi_intr_get_hilevel_pri()) {
3839 nv_cmn_err(CE_WARN, nvc, NULL,
3846 if (ddi_intr_add_handler(nvc->nvc_htable[x],
3847 nvc->nvc_interrupt, (caddr_t)nvc, NULL) != DDI_SUCCESS) {
3848 nv_cmn_err(CE_WARN, nvc, NULL,
3858 for (x = 0; x < nvc->nvc_intr_cnt; x++) {
3859 (void) ddi_intr_enable(nvc->nvc_htable[x]);
3869 (void) ddi_intr_free(nvc->nvc_htable[y]);
3872 kmem_free(nvc->nvc_htable, nvc->nvc_intr_size);
3882 nv_add_msi_intrs(nv_ctl_t *nvc)
3884 dev_info_t *devinfo = nvc->nvc_dip;
3888 NVLOG(NVDBG_INIT, nvc, NULL, "nv_add_msi_intrs", NULL);
3895 nv_cmn_err(CE_WARN, nvc, NULL,
3907 nv_cmn_err(CE_WARN, nvc, NULL,
3915 nv_cmn_err(CE_WARN, nvc, NULL,
3923 nvc->nvc_intr_size = count * sizeof (ddi_intr_handle_t);
3924 nvc->nvc_htable = kmem_alloc(nvc->nvc_intr_size, KM_SLEEP);
3926 rc = ddi_intr_alloc(devinfo, nvc->nvc_htable, DDI_INTR_TYPE_MSI,
3930 nv_cmn_err(CE_WARN, nvc, NULL,
3932 kmem_free(nvc->nvc_htable, nvc->nvc_intr_size);
3941 NVLOG(NVDBG_INIT, nvc, NULL,
3945 nvc->nvc_intr_cnt = actual;
3950 if (ddi_intr_get_pri(nvc->nvc_htable[0], &nvc->nvc_intr_pri) !=
3952 nv_cmn_err(CE_WARN, nvc, NULL, "ddi_intr_get_pri() failed");
3960 if (nvc->nvc_intr_pri >= ddi_intr_get_hilevel_pri()) {
3961 nv_cmn_err(CE_WARN, nvc, NULL,
3971 if (ddi_intr_add_handler(nvc->nvc_htable[x],
3972 nvc->nvc_interrupt, (caddr_t)nvc, NULL) != DDI_SUCCESS) {
3973 nv_cmn_err(CE_WARN, nvc, NULL,
3980 (void) ddi_intr_get_cap(nvc->nvc_htable[0], &nvc->nvc_intr_cap);
3982 if (nvc->nvc_intr_cap & DDI_INTR_FLAG_BLOCK) {
3983 (void) ddi_intr_block_enable(nvc->nvc_htable,
3984 nvc->nvc_intr_cnt);
3989 for (x = 0; x < nvc->nvc_intr_cnt; x++) {
3990 (void) ddi_intr_enable(nvc->nvc_htable[x]);
4001 (void) ddi_intr_free(nvc->nvc_htable[y]);
4004 kmem_free(nvc->nvc_htable, nvc->nvc_intr_size);
4012 nv_rem_intrs(nv_ctl_t *nvc)
4017 NVLOG(NVDBG_INIT, nvc, NULL, "nv_rem_intrs", NULL);
4023 for (i = 0; i < NV_MAX_PORTS(nvc); i++) {
4024 nvp = (&nvc->nvc_port[i]);
4026 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE);
4033 if ((nvc->nvc_intr_type == DDI_INTR_TYPE_MSI) &&
4034 (nvc->nvc_intr_cap & DDI_INTR_FLAG_BLOCK)) {
4035 (void) ddi_intr_block_disable(nvc->nvc_htable,
4036 nvc->nvc_intr_cnt);
4038 for (x = 0; x < nvc->nvc_intr_cnt; x++) {
4039 (void) ddi_intr_disable(nvc->nvc_htable[x]);
4043 for (x = 0; x < nvc->nvc_intr_cnt; x++) {
4044 (void) ddi_intr_remove_handler(nvc->nvc_htable[x]);
4045 (void) ddi_intr_free(nvc->nvc_htable[x]);
4048 kmem_free(nvc->nvc_htable, nvc->nvc_intr_size);
4057 nv_vcmn_err(int ce, nv_ctl_t *nvc, nv_port_t *nvp, const char *fmt, va_list ap,
4064 if (nvc) {
4066 ddi_get_instance(nvc->nvc_dip));
4067 dip = nvc->nvc_dip;
4119 nv_cmn_err(int ce, nv_ctl_t *nvc, nv_port_t *nvp, char *fmt, ...)
4124 nv_vcmn_err(ce, nvc, nvp, fmt, ap, B_TRUE);
4130 nv_log(nv_ctl_t *nvc, nv_port_t *nvp, const char *fmt, ...)
4136 nv_vcmn_err(CE_CONT, nvc, nvp, fmt, ap, B_FALSE);
4143 if (nvp == NULL && nvc == NULL) {
4150 if (nvp == NULL && nvc != NULL) {
4151 sata_vtrace_debug(nvc->nvc_dip, fmt, ap);
4158 * nvp is not NULL, but nvc might be. Reference nvp for both
5911 nv_ctl_t *nvc = nvp->nvp_ctlp;
5912 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
5913 uchar_t *bar5 = nvc->nvc_bar_addr[5];
5934 mutex_enter(&nvc->nvc_mutex);
5937 NVLOG(NVDBG_INTR, nvc, nvp,
5940 intr_status = nv_get8(nvc->nvc_bar_hdl[5],
5941 (uint8_t *)(nvc->nvc_ck804_int_status));
5945 nv_put8(nvc->nvc_bar_hdl[5],
5946 (uint8_t *)(nvc->nvc_ck804_int_status),
5949 NVLOG(NVDBG_INTR, nvc, nvp,
5956 NVLOG(NVDBG_INTR, nvc, nvp,
5966 NVLOG(NVDBG_INTR, nvc, nvp, "ck804_set_intr: NV_INTR_ENABLE",
5975 mutex_exit(&nvc->nvc_mutex);
5986 nv_ctl_t *nvc = nvp->nvp_ctlp;
5987 ddi_acc_handle_t bar5_hdl = nvc->nvc_bar_hdl[5];
6001 NVLOG(NVDBG_INTR, nvc, nvp, "mcp055_set_intr: enter flag: %d", flag);
6004 NVLOG(NVDBG_INTR, nvc, nvp,
6010 NVLOG(NVDBG_INTR, nvc, nvp, "mcp5x_set_intr: NV_INTR_ENABLE",
6018 NVLOG(NVDBG_INTR, nvc, nvp,
6384 nv_ctl_t *nvc;
6386 if ((nvc = (nv_ctl_t *)ddi_get_soft_state(nv_statep, instance)) == NULL)
6389 for (port = 0; port < NV_MAX_PORTS(nvc); port++) {
6390 nv_port_t *nvp = &(nvc->nvc_port[port]);
6398 (*(nvc->nvc_set_intr))(nvp, NV_INTR_DISABLE_NON_BLOCKING);
6447 nv_sgp_led_init(nv_ctl_t *nvc, ddi_acc_handle_t pci_conf_handle)
6461 nvc->nvc_sgp_csr = 0;
6462 nvc->nvc_sgp_cbp = NULL;
6463 nvc->nvc_sgp_cmn = NULL;
6469 if (ddi_getprop(DDI_DEV_T_ANY, nvc->nvc_dip, DDI_PROP_DONTPASS,
6477 if (nvc->nvc_mcp5x_flag != B_TRUE)
6486 if ((nvc->nvc_ctlr_num != 0) && (nvc->nvc_ctlr_num != 1))
6491 NVLOG(NVDBG_INIT, nvc, NULL,
6497 nvc->nvc_sgp_csr = csrp;
6500 nvc->nvc_sgp_cbp = (nv_sgp_cb_t *)psm_map_phys_new(cbp,
6504 if (nv_sgp_init(nvc) == NV_FAILURE) {
6505 nv_cmn_err(CE_WARN, nvc, NULL,
6535 nvc->nvc_sgp_cmn = NULL;
6536 nv_cmn_err(CE_WARN, nvc, NULL,
6548 nv_cmn_err(CE_WARN, nvc, NULL,
6553 nvc->nvc_sgp_cmn = cmn;
6556 cmn->nvs_in_use = (1 << nvc->nvc_ctlr_num);
6567 nvc->nvc_sgp_cbp->sgpio_sr = (uint64_t)cmn;
6569 nvc->nvc_sgp_cbp->sgpio_sr = (uint32_t)cmn;
6585 cmn->nvs_taskq = ddi_taskq_create(nvc->nvc_dip, tqname, 1,
6589 nv_cmn_err(CE_WARN, nvc, NULL,
6594 nv_sgp_activity_led_ctl, nvc, DDI_SLEEP);
6597 nvc->nvc_sgp_cmn = cmn;
6598 cmn->nvs_in_use |= (1 << nvc->nvc_ctlr_num);
6637 nv_sgp_init(nv_ctl_t *nvc)
6646 status = nv_sgp_csr_read(nvc);
6655 nv_sgp_csr_write(nvc, cmd);
6663 status = nv_sgp_csr_read(nvc);
6667 NVLOG(NVDBG_VERBOSE, nvc, NULL,
6677 NVLOG(NVDBG_VERBOSE, nvc, NULL,
6699 NVLOG(NVDBG_VERBOSE, nvc, NULL,
6713 drive_count = SGP_CR0_DRV_CNT(nvc->nvc_sgp_cbp->sgpio_cr0);
6715 NVLOG(NVDBG_INIT, nvc, NULL,
6720 NVLOG(NVDBG_INIT, nvc, NULL,
6722 nvc->nvc_ctlr_num, nvc->nvc_sgp_csr);
6728 nv_sgp_check_set_cmn(nv_ctl_t *nvc)
6730 nv_sgp_cmn_t *cmn = nvc->nvc_sgp_cmn;
6736 cmn->nvs_in_use |= (1 << nvc->nvc_ctlr_num);
6751 nv_sgp_csr_read(nv_ctl_t *nvc)
6753 return (inl(nvc->nvc_sgp_csr));
6765 nv_sgp_csr_write(nv_ctl_t *nvc, uint32_t val)
6767 outl(nvc->nvc_sgp_csr, val);
6775 nv_sgp_write_data(nv_ctl_t *nvc)
6783 nv_sgp_csr_write(nvc, cmd);
6789 status = nv_sgp_csr_read(nvc);
6820 nv_ctl_t *nvc = (nv_ctl_t *)arg;
6829 cmn = nvc->nvc_sgp_cmn;
6830 cbp = nvc->nvc_sgp_cbp;
6917 if (nv_sgp_write_data(nvc) == NV_FAILURE) {
6918 NVLOG(NVDBG_VERBOSE, nvc, NULL,
6939 nv_sgp_drive_connect(nv_ctl_t *nvc, int drive)
6943 if (nv_sgp_check_set_cmn(nvc) == NV_FAILURE)
6945 cmn = nvc->nvc_sgp_cmn;
6960 nv_sgp_drive_disconnect(nv_ctl_t *nvc, int drive)
6964 if (nv_sgp_check_set_cmn(nvc) == NV_FAILURE)
6966 cmn = nvc->nvc_sgp_cmn;
6981 nv_sgp_drive_active(nv_ctl_t *nvc, int drive)
6985 if (nv_sgp_check_set_cmn(nvc) == NV_FAILURE)
6987 cmn = nvc->nvc_sgp_cmn;
7003 nv_sgp_locate(nv_ctl_t *nvc, int drive, int value)
7006 volatile nv_sgp_cb_t *cb = nvc->nvc_sgp_cbp;
7009 if (nv_sgp_check_set_cmn(nvc) == NV_FAILURE)
7011 cmn = nvc->nvc_sgp_cmn;
7032 if (nv_sgp_write_data(nvc) == NV_FAILURE) {
7033 nv_cmn_err(CE_WARN, nvc, NULL,
7044 nv_sgp_error(nv_ctl_t *nvc, int drive, int value)
7047 volatile nv_sgp_cb_t *cb = nvc->nvc_sgp_cbp;
7050 if (nv_sgp_check_set_cmn(nvc) == NV_FAILURE)
7052 cmn = nvc->nvc_sgp_cmn;
7073 if (nv_sgp_write_data(nvc) == NV_FAILURE) {
7074 nv_cmn_err(CE_WARN, nvc, NULL,
7080 nv_sgp_cleanup(nv_ctl_t *nvc)
7085 volatile nv_sgp_cb_t *cb = nvc->nvc_sgp_cbp;
7086 nv_sgp_cmn_t *cmn = nvc->nvc_sgp_cmn;
7104 drive = SGP_CTLR_PORT_TO_DRV(nvc->nvc_ctlr_num, 0);
7109 drive = SGP_CTLR_PORT_TO_DRV(nvc->nvc_ctlr_num, 1);
7115 (void) nv_sgp_write_data(nvc);
7119 cmn->nvs_in_use &= ~(1 << nvc->nvc_ctlr_num);
7137 (void) nv_sgp_write_data(nvc);
7157 kmem_free(nvc->nvc_sgp_cmn, sizeof (nv_sgp_cmn_t));
7160 nvc->nvc_sgp_cmn = NULL;
7163 psm_unmap_phys((caddr_t)nvc->nvc_sgp_cbp, sizeof (nv_sgp_cb_t));