io/nxge/nxge_intr.c

30  * This file manages the interrupts for a hybrid I/O (hio) device.
31  * In the future, it may manage interrupts for all Neptune-based
75 	nxge_intr_t	*interrupts; /* The global interrupt data. */
102 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
106 	if ((status2 = ddi_intr_add_handler(interrupts->htable[vector],
115 	interrupts->intr_added++;
118 	if ((status2 = ddi_intr_enable(interrupts->htable[vector]))
127 		interrupts->intr_enabled = B_TRUE;
165 	nxge_intr_t	*interrupts; /* The global interrupt data. */
194 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
199 	if ((status2 = ddi_intr_disable(interrupts->htable[vector]))
208 	if ((status2 = ddi_intr_remove_handler(interrupts->htable[vector]))
217 		interrupts->intr_added--;
218 		if (interrupts->intr_added == 0)
219 			interrupts->intr_enabled = B_FALSE;
322 	nxge_intr_t	*interrupts; /* The global interrupt data. */
347 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
360 	if ((ddi_status = ddi_intr_add_handler(interrupts->htable[vector],
370 	interrupts->intr_added++;
373 	if ((ddi_status = ddi_intr_enable(interrupts->htable[vector]))
382 	interrupts->intr_enabled = B_TRUE;
385 	 * Note: RDC interrupts will be armed in nxge_m_start(). This
423 	nxge_intr_t	*interrupts; /* The global interrupt data. */
455 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
470 	if ((status2 = ddi_intr_disable(interrupts->htable[vector]))
480 	if ((status2 = ddi_intr_remove_handler(interrupts->htable[vector]))
492 		interrupts->intr_added--;
493 		if (interrupts->intr_added == 0)
494 			interrupts->intr_enabled = B_FALSE;
505  *	Initialize interrupts in a guest domain.
523 	nxge_intr_t	*interrupts;
535 	/* Look up the "interrupts" property. */
537 	    "interrupts", &prop_val, &prop_len)) != DDI_PROP_SUCCESS) {
539 		    "==> nxge_hio_intr_init(obp): no 'interrupts' property"));
544 	 * For each device assigned, the content of each interrupts
547 	 * Assignment of interrupts property is in the the following
566 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
568 	interrupts->intr_registered = B_FALSE;
569 	interrupts->intr_enabled = B_FALSE;
570 	interrupts->start_inum = 0;
573 	    nxge->dip, &interrupts->intr_types);
577 		    "types = 0x%x", ddi_status, interrupts->intr_types));
582 	    "returned 0x%x, types = 0x%x", ddi_status, interrupts->intr_types));
585 	interrupts->intr_type = DDI_INTR_TYPE_FIXED;
588 	intr_type = interrupts->intr_type;
600 	    "nxge_hio_intr_init: number of available interrupts: %d", navail));
612 	    "nxge_hio_intr_init: number of interrupts: %d", nintrs));
614 	interrupts->intr_size = navail * sizeof (ddi_intr_handle_t);
615 	interrupts->htable = kmem_alloc(interrupts->intr_size, KM_SLEEP);
620 	 * interrupts are are allocated. Otherwise, it fails.
625 	ddi_status = ddi_intr_alloc(nxge->dip, interrupts->htable, intr_type,
635 	    "nxge_hio_intr_init: number of interrupts allocated: %d", nactual));
641 	if ((ddi_status = ddi_intr_get_pri(interrupts->htable[0],
642 	    (uint_t *)&interrupts->pri)) != DDI_SUCCESS) {
648 	    "nxge_hio_intr_init: interrupt priority: %d", interrupts->pri));
651 	if ((ddi_status = ddi_intr_get_cap(interrupts->htable[0],
652 	    &interrupts->intr_cap)) != DDI_SUCCESS) {
659 	    interrupts->intr_cap));
661 	interrupts->intr_registered = B_TRUE;
671  *	Uninitialize interrupts in a guest domain.
686 	nxge_intr_t *interrupts;
693 	interrupts = (nxge_intr_t *)&nxge->nxge_intr_type;
696 	 * If necessary, disable any currently active interrupts.
698 	if (interrupts->intr_enabled) {
723 	 * Free all of our allocated interrupts.
727 		if (interrupts->htable[i])
728 			(void) ddi_intr_free(interrupts->htable[i]);
729 		interrupts->htable[i] = 0;
732 	interrupts->intr_registered = B_FALSE;
733 	KMEM_FREE(interrupts->htable, interrupts->intr_size);
734 	interrupts->htable = NULL;
900  *	Guest domains can only add interrupts for DMA channels.
901  *	They cannot access the MAC, MIF, or SYSERR interrupts.
950 	 * <hw_config.ldg> is a copy of the "interrupts" property.
1022  *	Manage a VLDG's interrupts.