nxge/npi/npi_zcp.c

324 			val.qw0.bits.ldw.rdc_tbl_offset =
325 			    sflow->qw0.bits.ldw.rdc_tbl_offset;
329 			val.qw0.bits.ldw.buf_size =
330 			    sflow->qw0.bits.ldw.buf_size;
334 			val.qw0.bits.ldw.num_buf = sflow->qw0.bits.ldw.num_buf;
338 			val.qw0.bits.ldw.ulp_end = sflow->qw0.bits.ldw.ulp_end;
342 			val.qw1.bits.ldw.ulp_end = sflow->qw1.bits.ldw.ulp_end;
346 			val.qw1.bits.ldw.ulp_end_en =
347 			    sflow->qw1.bits.ldw.ulp_end_en;
351 			val.qw1.bits.ldw.unmap_all_en =
352 			    sflow->qw1.bits.ldw.unmap_all_en;
356 			val.qw1.bits.ldw.tmode = sflow->qw1.bits.ldw.tmode;
360 			val.qw1.bits.ldw.skip = sflow->qw1.bits.ldw.skip;
364 			val.qw1.bits.ldw.ring_base =
365 			    sflow->qw1.bits.ldw.ring_base;
369 			val.qw2.bits.ldw.ring_base =
370 			    sflow->qw2.bits.ldw.ring_base;
374 			val.qw2.bits.ldw.ring_size =
375 			    sflow->qw2.bits.ldw.ring_size;
379 			val.qw2.bits.ldw.busy = sflow->qw2.bits.ldw.busy;
383 			val.qw3.bits.ldw.toq = sflow->qw3.bits.ldw.toq;
450 			val.qw0.bits.ldw.mapped_in =
451 			    dflow->qw0.bits.ldw.mapped_in;
455 			val.qw1.bits.ldw.anchor_seq =
456 			    dflow->qw1.bits.ldw.anchor_seq;
460 			val.qw2.bits.ldw.anchor_offset =
461 			    dflow->qw2.bits.ldw.anchor_offset;
465 			val.qw2.bits.ldw.anchor_buf =
466 			    dflow->qw2.bits.ldw.anchor_buf;
470 			val.qw2.bits.ldw.anchor_buf_flag =
471 			    dflow->qw2.bits.ldw.anchor_buf_flag;
475 			val.qw2.bits.ldw.unmap_on_left =
476 			    dflow->qw2.bits.ldw.unmap_on_left;
480 			val.qw2.bits.ldw.ulp_end_reached =
481 			    dflow->qw2.bits.ldw.ulp_end_reached;
485 			val.qw3.bits.ldw.err_stat =
486 			    dflow->qw3.bits.ldw.err_stat;
490 			val.qw3.bits.ldw.wr_ptr = dflow->qw3.bits.ldw.wr_ptr;
494 			val.qw3.bits.ldw.hoq = dflow->qw3.bits.ldw.hoq;
498 			val.qw3.bits.ldw.prefetch_on =
499 			    dflow->qw3.bits.ldw.prefetch_on;
640 			cfifo_reg.bits.ldw.reset_cfifo0 = 1;
642 			cfifo_reg.bits.ldw.reset_cfifo0 = 0;
646 			cfifo_reg.bits.ldw.reset_cfifo1 = 1;
648 			cfifo_reg.bits.ldw.reset_cfifo1 = 0;
651 			cfifo_reg.bits.ldw.reset_cfifo2 = 1;
653 			cfifo_reg.bits.ldw.reset_cfifo2 = 0;
656 			cfifo_reg.bits.ldw.reset_cfifo3 = 1;
658 			cfifo_reg.bits.ldw.reset_cfifo3 = 0;
691 	ram_ctl.bits.ldw.ram_sel = ram_sel;
692 	ram_ctl.bits.ldw.zcfid = flow_id;
693 	ram_ctl.bits.ldw.rdwr = ZCP_RAM_RD;
694 	ram_ctl.bits.ldw.cfifo = cfifo_entryn;
698 	if (ram_ctl.bits.ldw.busy != 0) {
711 	if (ram_ctl.bits.ldw.busy != 0)
732 	ram_ctl.bits.ldw.ram_sel = ram_sel;
733 	ram_ctl.bits.ldw.zcfid = flow_id;
734 	ram_ctl.bits.ldw.rdwr = ZCP_RAM_WR;
735 	ram_en.bits.ldw.be = byte_en;
736 	ram_ctl.bits.ldw.cfifo = cfifo_entryn;
753 	if (ram_ctl.bits.ldw.busy != 0)