nxge/npi/npi_rxdma.c

111 npi_rxdma_cfg_rdc_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op);
113 npi_rxdma_cfg_rdc_rcr_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op,
119  * Dumps the contents of rdc csrs and fzc registers
123  *         rdc:      RX DMA number
131 npi_rxdma_dump_rdc_regs(npi_handle_t handle, uint8_t rdc)
140 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
141 	if (!RXDMA_CHANNEL_VALID(rdc)) {
145 		    rdc));
154 	    rdc));
156 		RXDMA_REG_READ64(handle, rdc_dmc_offset[i], rdc, &value);
158 		    rdc);
166 	    rdc));
175  * Dumps the contents of rdc csrs and fzc registers
211  * per rdc config functions
214 npi_rxdma_cfg_logical_page_disable(npi_handle_t handle, uint8_t rdc,
220 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
221 	if (!RXDMA_CHANNEL_VALID(rdc)) {
225 		    rdc));
238 	valid_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VLD_REG, rdc);
253 npi_rxdma_cfg_logical_page(npi_handle_t handle, uint8_t rdc,
263 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
264 	if (!RXDMA_CHANNEL_VALID(rdc)) {
268 		    rdc));
281 	valid_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VLD_REG, rdc);
295 		mask_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_MASK1_REG, rdc);
296 		value_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VAL1_REG, rdc);
297 		reloc_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_RELO1_REG, rdc);
302 		mask_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_MASK2_REG, rdc);
303 		value_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_VAL2_REG, rdc);
304 		reloc_offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_RELO2_REG, rdc);
332 npi_rxdma_cfg_logical_page_handle(npi_handle_t handle, uint8_t rdc,
338 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
339 	if (!RXDMA_CHANNEL_VALID(rdc)) {
342 		    " Illegal RDC number %d \n", rdc));
349 	offset = REG_FZC_RDC_OFFSET(RX_LOG_PAGE_HDL_REG, rdc);
359 npi_rxdma_cfg_rdc_ctl(npi_handle_t handle, uint8_t rdc, uint8_t op)
365 	uint32_t error = NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RESET_ERR, rdc);
367 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
368 	if (!RXDMA_CHANNEL_VALID(rdc)) {
371 		    " Illegal RDC number %d \n", rdc));
378 			RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
382 			    rdc, cfg.value);
385 			RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
389 				RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
397 				    rdc));
403 			RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
407 			    rdc, cfg.value);
410 			RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
414 				RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
421 				    rdc));
431 			    rdc, cfg.value);
433 			RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
437 				RXDMA_REG_READ64(handle, RXDMA_CFIG1_REG, rdc,
444 				    rdc));
456 npi_rxdma_cfg_rdc_enable(npi_handle_t handle, uint8_t rdc)
458 	return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_ENABLE));
462 npi_rxdma_cfg_rdc_disable(npi_handle_t handle, uint8_t rdc)
464 	return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_DISABLE));
468 npi_rxdma_cfg_rdc_reset(npi_handle_t handle, uint8_t rdc)
470 	return (npi_rxdma_cfg_rdc_ctl(handle, rdc, RXDMA_OP_RESET));
475  * Set the default rdc for the port
480  *	rdc:	RX DMA Channel number
489 				    uint8_t portnm, uint8_t rdc)
495 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
496 	if (!RXDMA_CHANNEL_VALID(rdc)) {
500 		    rdc));
515 	cfg.bits.ldw.rdc = rdc;
521 npi_rxdma_cfg_rdc_rcr_ctl(npi_handle_t handle, uint8_t rdc,
526 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
527 	if (!RXDMA_CHANNEL_VALID(rdc)) {
531 		    rdc));
536 	RXDMA_REG_READ64(handle, RCRCFIG_B_REG, rdc, &rcr_cfgb.value);
557 		return (NPI_RXDMA_OPCODE_INVALID(rdc));
560 	RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, rdc, rcr_cfgb.value);
565 npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t handle, uint8_t rdc)
567 	return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
572 npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t handle, uint8_t rdc,
575 	return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
581 npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t handle, uint8_t rdc,
584 	return (npi_rxdma_cfg_rdc_rcr_ctl(handle, rdc,
594 npi_rxdma_cfg_rdc_ring(npi_handle_t handle, uint8_t rdc,
604 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
605 	if (!RXDMA_CHANNEL_VALID(rdc)) {
609 		    rdc));
686 		return (NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RBRSIZE_INVALID, rdc));
791 		return (NPI_RXDMA_ERROR_ENCODE(NPI_RXDMA_RCRSIZE_INVALID, rdc));
827 	RXDMA_REG_WRITE64(handle, RXDMA_CFIG1_REG, rdc, cfg1.value);
828 	RXDMA_REG_WRITE64(handle, RXDMA_CFIG2_REG, rdc, cfg2.value);
831 	RXDMA_REG_WRITE64(handle, RBR_CFIG_A_REG, rdc, cfga.value);
832 	RXDMA_REG_WRITE64(handle, RBR_CFIG_B_REG, rdc, cfgb.value);
834 	RXDMA_REG_WRITE64(handle, RCRCFIG_A_REG, rdc, rcr_cfga.value);
835 	RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, rdc, rcr_cfgb.value);
848  *	rdc:		RX DMA Channel number
857 npi_rxdma_red_discard_stat_get(npi_handle_t handle, uint8_t rdc,
862 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
863 	if (!RXDMA_CHANNEL_VALID(rdc)) {
867 		    rdc));
871 	offset = RDC_RED_RDC_DISC_REG(rdc);
878 		    rdc));
893  *	rdc:		RX DMA Channel number
901 npi_rxdma_red_discard_oflow_clear(npi_handle_t handle, uint8_t rdc)
907 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
908 	if (!RXDMA_CHANNEL_VALID(rdc)) {
912 			    rdc));
916 	offset = RDC_RED_RDC_DISC_REG(rdc);
923 			    rdc));
932  * Gets the current discrad count for the rdc due to
938  *	rdc:		RX DMA Channel number
947 npi_rxdma_misc_discard_stat_get(npi_handle_t handle, uint8_t rdc,
950 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
951 	if (!RXDMA_CHANNEL_VALID(rdc)) {
955 		    rdc));
959 	RXDMA_REG_READ64(handle, RXMISC_DISCARD_REG, rdc, &cnt->value);
965 		    rdc));
967 		RXDMA_REG_WRITE64(handle, RXMISC_DISCARD_REG, rdc, cnt->value);
978  * for the rdc
982  *	rdc:		RX DMA Channel number
990 npi_rxdma_misc_discard_oflow_clear(npi_handle_t handle, uint8_t rdc)
994 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
995 	if (!RXDMA_CHANNEL_VALID(rdc)) {
999 		    rdc));
1003 	RXDMA_REG_READ64(handle, RXMISC_DISCARD_REG, rdc, &cnt.value);
1009 		    rdc));
1011 		RXDMA_REG_WRITE64(handle, RXMISC_DISCARD_REG, rdc, cnt.value);
1395 npi_rxdma_cfg_wred_param(npi_handle_t handle, uint8_t rdc,
1401 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
1402 	if (!RXDMA_CHANNEL_VALID(rdc)) {
1406 		    rdc));
1414 	offset = RDC_RED_RDC_PARA_REG(rdc);
1502 		rdc_tbl.bits.ldw.rdc = set[cursor++];
1531 			    uint8_t table, uint8_t rdc)
1542 		    rdc));
1547 	tbl_reg.bits.ldw.rdc = rdc;
1588 npi_rxdma_rdc_rbr_stat_get(npi_handle_t handle, uint8_t rdc,
1592 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
1593 	if (!RXDMA_CHANNEL_VALID(rdc)) {
1597 		    rdc));
1601 	RXDMA_REG_READ64(handle, RBR_STAT_REG, rdc, &rbr_stat->value);
1611  *	rdc:		RX DMA Channel number
1620 			    uint8_t rdc, addr44_t *hdptr)
1625 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
1626 	if (!RXDMA_CHANNEL_VALID(rdc)) {
1630 		    rdc));
1635 	RXDMA_REG_READ64(handle, RBR_HDH_REG, rdc, &hh_ptr.value);
1636 	RXDMA_REG_READ64(handle, RBR_HDL_REG, rdc, &hl_ptr.value);
1644 npi_rxdma_rdc_rcr_qlen_get(npi_handle_t handle, uint8_t rdc,
1650 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
1651 	if (!RXDMA_CHANNEL_VALID(rdc)) {
1655 		    rdc));
1659 	RXDMA_REG_READ64(handle, RCRSTAT_A_REG, rdc, &stats.value);
1664 	    rdc, *rcr_qlen, stats.bits.ldw.qlen));
1670 			    uint8_t rdc, addr44_t *tail_addr)
1676 	ASSERT(RXDMA_CHANNEL_VALID(rdc));
1677 	if (!RXDMA_CHANNEL_VALID(rdc)) {
1681 		    rdc));
1686 	RXDMA_REG_READ64(handle, RCRSTAT_B_REG, rdc, &th_ptr.value);
1687 	RXDMA_REG_READ64(handle, RCRSTAT_C_REG, rdc, &tl_ptr.value);
1693 	    rdc, tl_ptr.value,