nxge/npi/npi_mac.c

61 	} while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay);	  \
574 	pcs_cfg.bits.w0.mask = 0;
588 	pcs_cfg.bits.w0.mask = 1;
602 	xpcs_mask1.bits.w0.csr_rx_link_stat = 1;
616 	xpcs_mask1.bits.w0.csr_rx_link_stat = 0;
631 	mif_cfg.bits.w0.phy_addr = portn;
632 	mif_cfg.bits.w0.poll_en = 0;
775  * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses,
3106 	frame.bits.w0.st = FRAME45_ST;		/* Clause 45	*/
3107 	frame.bits.w0.op = FRAME45_OP_ADDR;	/* Select address	*/
3108 	frame.bits.w0.phyad = portn;		/* Port number	*/
3109 	frame.bits.w0.regad = device;		/* Device number	*/
3110 	frame.bits.w0.ta_msb = 1;
3111 	frame.bits.w0.ta_lsb = 0;
3112 	frame.bits.w0.data = xcvr_reg;	/* register address */
3130 	frame.bits.w0.st = FRAME45_ST; /* Clause 45 */
3131 	frame.bits.w0.op = FRAME45_OP_READ; /* Read */
3132 	frame.bits.w0.phyad = portn; /* Port Number */
3133 	frame.bits.w0.regad = device; /* Device Number */
3134 	frame.bits.w0.ta_msb = 1;
3135 	frame.bits.w0.ta_lsb = 0;
3148 	*value = frame.bits.w0.data;
3167 	frame.bits.w0.st = 0x1; /* Clause 22 */
3168 	frame.bits.w0.op = 0x2;
3169 	frame.bits.w0.phyad = portn;
3170 	frame.bits.w0.regad = xcvr_reg;
3171 	frame.bits.w0.ta_msb = 1;
3172 	frame.bits.w0.ta_lsb = 0;
3181 	*value = frame.bits.w0.data;
3184 	    xcvr_reg, frame.bits.w0.data));
3197 	frame.bits.w0.st = FRAME45_ST; /* Clause 45 */
3198 	frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */
3199 	frame.bits.w0.phyad = portn; /* Port Number */
3200 	frame.bits.w0.regad = device; /* Device Number */
3201 	frame.bits.w0.ta_msb = 1;
3202 	frame.bits.w0.ta_lsb = 0;
3203 	frame.bits.w0.data = xcvr_reg;	/* register address */
3221 	frame.bits.w0.st = FRAME45_ST; /* Clause 45 */
3222 	frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */
3223 	frame.bits.w0.phyad = portn; /* Port number   */
3224 	frame.bits.w0.regad = device; /* Device number */
3225 	frame.bits.w0.ta_msb = 1;
3226 	frame.bits.w0.ta_lsb = 0;
3227 	frame.bits.w0.data = value;
3254 	frame.bits.w0.st = 0x1; /* Clause 22 */
3255 	frame.bits.w0.op = 0x1;
3256 	frame.bits.w0.phyad = portn;
3257 	frame.bits.w0.regad = xcvr_reg;
3258 	frame.bits.w0.ta_msb = 1;
3259 	frame.bits.w0.ta_lsb = 0;
3260 	frame.bits.w0.data = value;
3303 		if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) &&
3304 		    (pcs_stat_mc.bits.w0.word_sync != 0)) {
3305 			pcs_stat.bits.w0.link_stat = 1;
3306 		} else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) {
3307 			pcs_stat.bits.w0.link_stat = 0;
3315 		esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex;
3316 		esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex;
3323 		anar.bits.cap_pause = pcs_anar.bits.w0.pause;
3324 		anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause;
3330 		anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause;
3331 		anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause;
3338 		aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex |
3339 		    pcs_anar.bits.w0.half_duplex;
3346 		gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex;
3347 		gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex;
3381 		pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause;
3382 		pcs_anar.bits.w0.pause = anar.bits.cap_pause;
3390 		pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx;
3391 		pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx;
3425 	mif_cfg.bits.w0.phy_addr = portn;		/* Port number */
3426 	mif_cfg.bits.w0.reg_addr = xcvr_reg;		/* Register address */
3427 	mif_cfg.bits.w0.indirect_md = 0; 		/* Clause 22 */
3428 	mif_cfg.bits.w0.poll_en = 1;
3448 	frame.bits.w0.st = 0;		/* Clause 45 */
3449 	frame.bits.w0.op = 0;		/* Select address */
3450 	frame.bits.w0.phyad = portn;	/* Port number */
3451 	frame.bits.w0.regad = device;	/* Device number */
3452 	frame.bits.w0.ta_msb = 1;
3453 	frame.bits.w0.ta_lsb = 0;
3454 	frame.bits.w0.data = xcvr_reg;	/* register address */
3465 	mif_cfg.bits.w0.phy_addr = portn;		/* Port number */
3466 	mif_cfg.bits.w0.reg_addr = device;		/* Register address */
3467 	mif_cfg.bits.w0.indirect_md = 1; 		/* Clause 45 */
3468 	mif_cfg.bits.w0.poll_en = 1;
3484 	mif_cfg.bits.w0.indirect_md = on_off;
3494 	mif_cfg.bits.w0.atca_ge = on_off;