Lines Matching refs:bits
237 (tctl.bits.ldw.stat != TCAM_CTL_RWC_RWC_STAT)) {
257 (tctl.bits.ldw.match != TCAM_CTL_RWC_RWC_MATCH)) {
305 * Class field is bits [195:191].
314 tctl.bits.ldw.location = location;
315 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_WR;
361 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_CMP;
373 if (tctl_stat.bits.ldw.match == TCAM_CTL_RWC_RWC_MATCH) {
374 return (uint32_t)(tctl_stat.bits.ldw.location);
406 tctl.bits.ldw.location = location;
407 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_RD;
476 tctl.bits.ldw.location = location;
477 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_WR;
521 tctl.bits.ldw.location = location;
522 tctl.bits.ldw.rwc = TCAM_CTL_RWC_RAM_WR;
565 tctl.bits.ldw.location = location;
566 tctl.bits.ldw.rwc = TCAM_CTL_RWC_RAM_RD;
593 * Corresponds to last 20 bits of H1 value
668 addr.bits.ldw.autoinc = autoinc;
669 addr.bits.ldw.addr = location;
692 * Corresponds to last 20 bits of H1 value
762 addr.bits.ldw.autoinc = autoinc;
763 addr.bits.ldw.addr = location;
811 addr.bits.ldw.addr = location;
831 * pointed by the last 20 bits of H1. Effectively, this accesses
848 * Bucket = [19:15][14:0] (20 bits of H1)
875 addr.bits.ldw.addr = location;
892 * pointed by the last 20 bits of H1. Effectively, this accesses
909 * Bucket = [19:15][14:0] (20 bits of H1)
936 addr.bits.ldw.addr = location;
984 sel.bits.ldw.mask = base_mask;
985 sel.bits.ldw.base = base_reloc;
986 sel.bits.ldw.ext = BIT_DISABLE; /* disable */
1025 sel.bits.ldw.ext = BIT_ENABLE; /* enable */
1061 sel.bits.ldw.ext = BIT_DISABLE; /* disable */
1081 fflp_cfg.bits.ldw.errordis = BIT_ENABLE;
1102 fflp_cfg.bits.ldw.errordis = BIT_DISABLE;
1124 fflp_cfg.bits.ldw.llcsnap = BIT_ENABLE;
1147 fflp_cfg.bits.ldw.llcsnap = BIT_DISABLE;
1193 refresh_timer_reg.bits.ldw.min = min;
1194 refresh_timer_reg.bits.ldw.max = max;
1205 * err_stat Pointer to return Error bits
1232 err_stat->syndrome = err_log2.bits.ldw.syndrome;
1233 err_stat->subarea = err_log2.bits.ldw.subarea;
1234 err_stat->h1 = err_log2.bits.ldw.h1;
1235 err_stat->multi_bit = err_log1.bits.ldw.mult_bit;
1236 err_stat->multi_lkup = err_log1.bits.ldw.mult_lk;
1237 err_stat->ecc_err = err_log1.bits.ldw.ecc_err;
1238 err_stat->uncor_err = err_log1.bits.ldw.cu;
1255 * err_stat Pointer to return Error bits
1282 if (err_log.bits.ldw.pio_err == BIT_ENABLE) {
1285 err_stat->syndrome = err_log.bits.ldw.syndrome;
1286 err_stat->addr = err_log.bits.ldw.fcram_addr;
1367 if (err_log.bits.ldw.err == BIT_ENABLE) {
1370 if (err_log.bits.ldw.p_ecc) {
1378 err_stat->syndrome = err_log.bits.ldw.syndrome;
1379 err_stat->location = err_log.bits.ldw.addr;
1382 err_stat->multi_lkup = err_log.bits.ldw.mult;
1427 * tst0->synd (8bits) are set to select the syndrome bits
1432 * syndrome_bits: Syndrome bits to select bits to be xor'ed
1449 tst0.bits.ldw.syndrome_mask = syndrome_bits;
1461 * bits [63:0] are set to select the data bits to be xor'ed
1465 * data: data bits to select bits to be xor'ed
1478 fcram_err_tst1_t tst1; /* for data bits [31:0] */
1479 fcram_err_tst2_t tst2; /* for data bits [63:32] */
1485 tst1.bits.ldw.dat = data->bits.ldw.dat;
1486 tst2.bits.ldw.dat = data->bits.hdw.dat;
1554 cfg.bits.ldw.vlanrdctbln0 = rdc_table;
1556 cfg.bits.ldw.vpr0 = BIT_ENABLE;
1558 cfg.bits.ldw.vpr0 = BIT_DISABLE;
1559 /* set the parity bits */
1560 parity_bit = vlan_parity[cfg.bits.ldw.vlanrdctbln0] +
1561 vlan_parity[cfg.bits.ldw.vlanrdctbln1] +
1562 cfg.bits.ldw.vpr0 + cfg.bits.ldw.vpr1;
1563 cfg.bits.ldw.parity0 = parity_bit & 0x1;
1566 cfg.bits.ldw.vlanrdctbln1 = rdc_table;
1568 cfg.bits.ldw.vpr1 = BIT_ENABLE;
1570 cfg.bits.ldw.vpr1 = BIT_DISABLE;
1571 /* set the parity bits */
1572 parity_bit = vlan_parity[cfg.bits.ldw.vlanrdctbln0] +
1573 vlan_parity[cfg.bits.ldw.vlanrdctbln1] +
1574 cfg.bits.ldw.vpr0 + cfg.bits.ldw.vpr1;
1575 cfg.bits.ldw.parity0 = parity_bit & 0x1;
1579 cfg.bits.ldw.vlanrdctbln2 = rdc_table;
1581 cfg.bits.ldw.vpr2 = BIT_ENABLE;
1583 cfg.bits.ldw.vpr2 = BIT_DISABLE;
1584 /* set the parity bits */
1585 parity_bit = vlan_parity[cfg.bits.ldw.vlanrdctbln2] +
1586 vlan_parity[cfg.bits.ldw.vlanrdctbln3] +
1587 cfg.bits.ldw.vpr2 + cfg.bits.ldw.vpr3;
1588 cfg.bits.ldw.parity1 = parity_bit & 0x1;
1592 cfg.bits.ldw.vlanrdctbln3 = rdc_table;
1594 cfg.bits.ldw.vpr3 = BIT_ENABLE;
1596 cfg.bits.ldw.vpr3 = BIT_DISABLE;
1597 /* set the parity bits */
1598 parity_bit = vlan_parity[cfg.bits.ldw.vlanrdctbln2] +
1599 vlan_parity[cfg.bits.ldw.vlanrdctbln3] +
1600 cfg.bits.ldw.vpr2 + cfg.bits.ldw.vpr3;
1601 cfg.bits.ldw.parity1 = parity_bit & 0x1;
1662 cfg.bits.ldw.vpr0 = BIT_ENABLE;
1664 cfg.bits.ldw.vpr0 = BIT_DISABLE;
1668 cfg.bits.ldw.vpr1 = BIT_ENABLE;
1670 cfg.bits.ldw.vpr1 = BIT_DISABLE;
1674 cfg.bits.ldw.vpr2 = BIT_ENABLE;
1676 cfg.bits.ldw.vpr2 = BIT_DISABLE;
1680 cfg.bits.ldw.vpr3 = BIT_ENABLE;
1682 cfg.bits.ldw.vpr3 = BIT_DISABLE;
1689 cfg.bits.ldw.parity1++;
1691 cfg.bits.ldw.parity0++;
1763 if (err_log.bits.ldw.err == BIT_ENABLE) {
1766 err_stat->multi = err_log.bits.ldw.m_err;
1767 err_stat->addr = err_log.bits.ldw.addr;
1768 err_stat->data = err_log.bits.ldw.data;
1851 cls_cfg.bits.ldw.etype = enet_type;
1852 cls_cfg.bits.ldw.valid = BIT_DISABLE;
1887 cls_cfg.bits.ldw.valid = BIT_ENABLE;
1922 cls_cfg.bits.ldw.valid = BIT_DISABLE;
1936 * tos: IP TOS bits
1937 * tos_mask: IP TOS bits mask. bits with mask bits set will be used
1964 ip_cls_cfg.bits.ldw.pid = proto;
1965 ip_cls_cfg.bits.ldw.ipver = ver;
1966 ip_cls_cfg.bits.ldw.tos = tos;
1967 ip_cls_cfg.bits.ldw.tosmask = tos_mask;
1968 ip_cls_cfg.bits.ldw.valid = 0;
2023 ip_cls_cfg.bits.ldw.valid = 0;
2108 ip_cls_cfg.bits.ldw.valid = 1;
2145 ip_cls_cfg.bits.ldw.valid = 0;
2160 * cfg: Configuration bits:
2200 tcam_cls_cfg.bits.ldw.discard = 1;
2204 tcam_cls_cfg.bits.ldw.ipaddr = 1;
2208 tcam_cls_cfg.bits.ldw.ipaddr = 0;
2212 tcam_cls_cfg.bits.ldw.tsel = 1;
2230 * cfg: Configuration bits:
2266 flow_cfg_reg.bits.ldw.proto = 1;
2270 flow_cfg_reg.bits.ldw.l4_1 = 2;
2272 flow_cfg_reg.bits.ldw.l4_1 = 3;
2276 flow_cfg_reg.bits.ldw.l4_0 = 2;
2278 flow_cfg_reg.bits.ldw.l4_0 = 3;
2282 flow_cfg_reg.bits.ldw.ipda = BIT_ENABLE;
2286 flow_cfg_reg.bits.ldw.ipsa = BIT_ENABLE;
2290 flow_cfg_reg.bits.ldw.vlan = BIT_ENABLE;
2294 flow_cfg_reg.bits.ldw.l2da = BIT_ENABLE;
2298 flow_cfg_reg.bits.ldw.port = BIT_ENABLE;
2337 if (flow_cfg_reg.bits.ldw.proto) {
2341 if (flow_cfg_reg.bits.ldw.l4_1 == 2) {
2345 if (flow_cfg_reg.bits.ldw.l4_1 == 3) {
2350 if (flow_cfg_reg.bits.ldw.l4_0 == 2) {
2354 if (flow_cfg_reg.bits.ldw.l4_0 == 3) {
2359 if (flow_cfg_reg.bits.ldw.ipda) {
2363 if (flow_cfg_reg.bits.ldw.ipsa) {
2367 if (flow_cfg_reg.bits.ldw.vlan) {
2371 if (flow_cfg_reg.bits.ldw.l2da) {
2375 if (flow_cfg_reg.bits.ldw.port) {
2398 * cfg: Configuration bits:
2441 flow_cfg_reg.bits.ldw.l4_xor = cfg->l4_xor_sel;
2444 flow_cfg_reg.bits.ldw.l4_mode = 1;
2447 flow_cfg_reg.bits.ldw.sym = 1;
2450 flow_cfg_reg.bits.ldw.proto = 1;
2454 flow_cfg_reg.bits.ldw.l4_1 = 2;
2456 flow_cfg_reg.bits.ldw.l4_1 = 3;
2460 flow_cfg_reg.bits.ldw.l4_0 = 2;
2462 flow_cfg_reg.bits.ldw.l4_0 = 3;
2466 flow_cfg_reg.bits.ldw.ipda = BIT_ENABLE;
2470 flow_cfg_reg.bits.ldw.ipsa = BIT_ENABLE;
2474 flow_cfg_reg.bits.ldw.vlan = BIT_ENABLE;
2478 flow_cfg_reg.bits.ldw.l2da = BIT_ENABLE;
2482 flow_cfg_reg.bits.ldw.port = BIT_ENABLE;
2514 if (enable && flow_cfg_reg.bits.ldw.sym == 0) {
2515 flow_cfg_reg.bits.ldw.sym = 1;
2517 } else if (!enable && flow_cfg_reg.bits.ldw.sym == 1) {
2518 flow_cfg_reg.bits.ldw.sym = 0;
2564 cfg->l4_xor_sel = flow_cfg_reg.bits.ldw.l4_xor;
2566 if (flow_cfg_reg.bits.ldw.l4_mode)
2569 if (flow_cfg_reg.bits.ldw.sym)
2572 if (flow_cfg_reg.bits.ldw.proto) {
2576 if (flow_cfg_reg.bits.ldw.l4_1 == 2) {
2580 if (flow_cfg_reg.bits.ldw.l4_1 == 3) {
2585 if (flow_cfg_reg.bits.ldw.l4_0 == 2) {
2589 if (flow_cfg_reg.bits.ldw.l4_0 == 3) {
2594 if (flow_cfg_reg.bits.ldw.ipda) {
2598 if (flow_cfg_reg.bits.ldw.ipsa) {
2602 if (flow_cfg_reg.bits.ldw.vlan) {
2606 if (flow_cfg_reg.bits.ldw.l2da) {
2610 if (flow_cfg_reg.bits.ldw.port) {
2648 if (tcam_cls_cfg.bits.ldw.discard)
2651 if (tcam_cls_cfg.bits.ldw.ipaddr) {
2656 if (tcam_cls_cfg.bits.ldw.tsel) {
2695 fflp_cfg.bits.ldw.fflpinitdone = 0;
2696 fflp_cfg.bits.ldw.fcramratio = access_ratio;
2699 fflp_cfg.bits.ldw.fflpinitdone = 1;
2732 fflp_cfg.bits.ldw.fflpinitdone = 0;
2733 fflp_cfg.bits.ldw.camratio = access_ratio;
2736 fflp_cfg.bits.ldw.camlatency = TCAM_DEFAULT_LATENCY;
2739 fflp_cfg.bits.ldw.fflpinitdone = 1;
2766 h1_cfg.bits.ldw.init_value = init_value;
2794 h2_cfg.bits.ldw.init_value = init_value;
2827 /* These bits have to be configured before FCRAM reset is issued */
2829 fflp_cfg.bits.ldw.pio_fio_rst = 1;
2834 fflp_cfg.bits.ldw.pio_fio_rst = 0;
2836 fflp_cfg.bits.ldw.fcramqs = qs;
2837 fflp_cfg.bits.ldw.fcramoutdr = strength;
2838 fflp_cfg.bits.ldw.fflpinitdone = 1;
2854 fflp_cfg.bits.ldw.fflpinitdone = 1;
2870 fflp_cfg.bits.ldw.fflpinitdone = 0;
2889 fflp_cfg.bits.ldw.tcam_disable = 0;
2909 fflp_cfg.bits.ldw.tcam_disable = 1;
2961 * Read vlan error bits
2970 * clear vlan error bits
2977 p_err.bits.ldw.m_err = 0;
2978 p_err.bits.ldw.err = 0;
2984 * Read TCAM error bits
2993 * clear TCAM error bits
3001 p_err.bits.ldw.p_ecc = 0;
3002 p_err.bits.ldw.mult = 0;
3003 p_err.bits.ldw.err = 0;
3009 * Read FCRAM error bits
3022 * clear FCRAM error bits
3031 p_err.bits.ldw.pio_err = 0;
3040 * Read FCRAM lookup error log1 bits
3051 * Read FCRAM lookup error log2 bits