Lines Matching refs:UNM_NIC_REG
36 #define UNM_NIC_REG(X) (NIC_CRB_BASE+(X))
41 #define CRB_CMD_PRODUCER_OFFSET UNM_NIC_REG(0x08)
42 #define CRB_CMD_CONSUMER_OFFSET UNM_NIC_REG(0x0c)
44 #define CRB_PAUSE_ADDR_LO UNM_NIC_REG(0x10)
45 #define CRB_PAUSE_ADDR_HI UNM_NIC_REG(0x14)
46 #define NX_CDRP_CRB_OFFSET UNM_NIC_REG(0x18)
47 #define NX_ARG1_CRB_OFFSET UNM_NIC_REG(0x1c)
48 #define NX_ARG2_CRB_OFFSET UNM_NIC_REG(0x20)
49 #define NX_ARG3_CRB_OFFSET UNM_NIC_REG(0x24)
50 #define NX_SIGN_CRB_OFFSET UNM_NIC_REG(0x28)
51 #define CRB_CMDPEG_CMDRING UNM_NIC_REG(0x38)
52 #define CRB_HOST_DUMMY_BUF_ADDR_HI UNM_NIC_REG(0x3c)
53 #define CRB_HOST_DUMMY_BUF_ADDR_LO UNM_NIC_REG(0x40)
54 #define CRB_CMDPEG_STATE UNM_NIC_REG(0x50)
56 #define CRB_GLOBAL_INT_COAL UNM_NIC_REG(0x64)
57 #define CRB_INT_COAL_MODE UNM_NIC_REG(0x68)
58 #define CRB_MAX_RCV_BUFS UNM_NIC_REG(0x6c)
59 #define CRB_TX_INT_THRESHOLD UNM_NIC_REG(0x70)
60 #define CRB_RX_PKT_TIMER UNM_NIC_REG(0x74)
61 #define CRB_TX_PKT_TIMER UNM_NIC_REG(0x78)
62 #define CRB_RX_PKT_CNT UNM_NIC_REG(0x7c)
63 #define CRB_RX_TMR_CNT UNM_NIC_REG(0x80)
64 #define CRB_RCV_INTR_COUNT UNM_NIC_REG(0x84)
66 #define CRB_XG_STATE UNM_NIC_REG(0x94)
68 #define CRB_XG_STATE_P3 UNM_NIC_REG(0x98)
70 #define CRB_TX_STATE UNM_NIC_REG(0xac)
71 #define CRB_TX_COUNT UNM_NIC_REG(0xb0)
72 #define CRB_RX_STATE UNM_NIC_REG(0xb4)
73 #define CRB_RX_PERF_DEBUG_1 UNM_NIC_REG(0xb8)
75 #define CRB_RX_LRO_CONTROL UNM_NIC_REG(0xbc)
77 #define CRB_MPORT_MODE UNM_NIC_REG(0xc4)
78 #define CRB_INT_VECTOR UNM_NIC_REG(0xd4)
79 #define CRB_PF_LINK_SPEED_1 UNM_NIC_REG(0xe8)
80 #define CRB_PF_LINK_SPEED_2 UNM_NIC_REG(0xec)
81 #define CRB_HOST_DUMMY_BUF UNM_NIC_REG(0xfc)
83 #define CRB_SCRATCHPAD_TEST UNM_NIC_REG(0x280)
85 #define CRB_RCVPEG_STATE UNM_NIC_REG(0x13c)
90 #define CRB_CMD_PRODUCER_OFFSET_1 UNM_NIC_REG(0x1ac)
91 #define CRB_CMD_CONSUMER_OFFSET_1 UNM_NIC_REG(0x1b0)
92 #define CRB_TEMP_STATE UNM_NIC_REG(0x1b4)
93 #define CRB_CMD_PRODUCER_OFFSET_2 UNM_NIC_REG(0x1b8)
94 #define CRB_CMD_CONSUMER_OFFSET_2 UNM_NIC_REG(0x1bc)
96 #define CRB_CMD_PRODUCER_OFFSET_3 UNM_NIC_REG(0x1d0)
97 #define CRB_CMD_CONSUMER_OFFSET_3 UNM_NIC_REG(0x1d4)
107 #define CRB_SW_INT_MASK_0 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0)
108 #define CRB_SW_INT_MASK_1 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1)
109 #define CRB_SW_INT_MASK_2 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2)
110 #define CRB_SW_INT_MASK_3 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3)
111 #define CRB_SW_INT_MASK_4 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4)
112 #define CRB_SW_INT_MASK_5 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5)
113 #define CRB_SW_INT_MASK_6 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6)
114 #define CRB_SW_INT_MASK_7 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7)
116 #define CRB_NIC_DEBUG_STRUCT_BASE UNM_NIC_REG(0x288)
122 #define CRB_NIC_CAPABILITIES_HOST UNM_NIC_REG(0x1a8)
123 #define CRB_NIC_MSI_MODE_HOST UNM_NIC_REG(0x270)
127 #define CRB_EPG_QUEUE_BUSY_COUNT UNM_NIC_REG(0x200)
129 #define CRB_V2P_0 UNM_NIC_REG(0x290)
130 #define CRB_V2P_1 UNM_NIC_REG(0x294)
131 #define CRB_V2P_2 UNM_NIC_REG(0x298)
132 #define CRB_V2P_3 UNM_NIC_REG(0x29c)
134 #define CRB_DRIVER_VERSION UNM_NIC_REG(0x2a0)
136 #define CRB_CNT_DBG1 UNM_NIC_REG(0x2a4)
137 #define CRB_CNT_DBG2 UNM_NIC_REG(0x2a8)
138 #define CRB_CNT_DBG3 UNM_NIC_REG(0x2ac)