io/igb/igb_82575.c

95 	struct e1000_phy_info *phy = &hw->phy;
100 	if (hw->phy.media_type != e1000_media_type_copper) {
101 		phy->type = e1000_phy_none;
105 	phy->ops.power_up = e1000_power_up_phy_copper;
106 	phy->ops.power_down = e1000_power_down_phy_copper_82575;
108 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
109 	phy->reset_delay_us = 100;
111 	phy->ops.acquire = e1000_acquire_phy_82575;
112 	phy->ops.check_reset_block = e1000_check_reset_block_generic;
113 	phy->ops.commit = e1000_phy_sw_reset_generic;
114 	phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
115 	phy->ops.release = e1000_release_phy_82575;
118 		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
119 		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
120 		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
122 		phy->ops.reset = e1000_phy_hw_reset_generic;
123 		phy->ops.read_reg = e1000_read_phy_reg_82580;
124 		phy->ops.write_reg = e1000_write_phy_reg_82580;
126 		phy->ops.reset = e1000_phy_hw_reset_generic;
127 		phy->ops.read_reg = e1000_read_phy_reg_igp;
128 		phy->ops.write_reg = e1000_write_phy_reg_igp;
131 	/* Set phy->phy_addr and phy->id. */
134 	/* Verify phy id and set remaining function pointers */
135 	switch (phy->id) {
137 		phy->type = e1000_phy_m88;
138 		phy->ops.check_polarity = e1000_check_polarity_m88;
139 		phy->ops.get_info = e1000_get_phy_info_m88;
140 		phy->ops.get_cable_length = e1000_get_cable_length_m88;
141 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
145 		phy->type = e1000_phy_igp_3;
146 		phy->ops.check_polarity = e1000_check_polarity_igp;
147 		phy->ops.get_info = e1000_get_phy_info_igp;
148 		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
149 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
150 		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
151 		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
154 		phy->type = e1000_phy_82580;
155 		phy->ops.check_polarity = e1000_check_polarity_82577;
156 		phy->ops.force_speed_duplex =
158 		phy->ops.get_cable_length = e1000_get_cable_length_82577;
159 		phy->ops.get_info = e1000_get_phy_info_82577;
249 	hw->phy.media_type = e1000_media_type_copper;
260 		hw->phy.media_type = e1000_media_type_internal_serdes;
309 	    (hw->phy.media_type == e1000_media_type_copper)
344 	/* set lan id for port to determine which phy lock to use */
363 	hw->phy.ops.init_params = e1000_init_phy_params_82575;
433 	ret_val = hw->phy.ops.acquire(hw);
439 	hw->phy.ops.release(hw);
466 	ret_val = hw->phy.ops.acquire(hw);
472 	hw->phy.ops.release(hw);
488 	struct e1000_phy_info *phy = &hw->phy;
499 	 * work.  The result of this function should mean phy->phy_addr
500 	 * and phy->id are set correctly.
503 		phy->addr = 1;
508 	/* Power on sgmii phy if it is disabled */
519 	for (phy->addr = 1; phy->addr < 8; phy->addr++) {
524 			    phy->addr);
533 			    phy->addr);
538 	if (phy->addr == 8) {
539 		phy->addr = 0;
572 	if (!(hw->phy.ops.write_reg))
579 	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
583 	ret_val = hw->phy.ops.commit(hw);
605 	struct e1000_phy_info *phy = &hw->phy;
611 	if (!(hw->phy.ops.read_reg))
614 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
620 		ret_val = phy->ops.write_reg(hw,
627 		ret_val = phy->ops.read_reg(hw,
631 		ret_val = phy->ops.write_reg(hw,
638 		ret_val = phy->ops.write_reg(hw,
647 		if (phy->smart_speed == e1000_smart_speed_on) {
648 			ret_val = phy->ops.read_reg(hw,
655 			ret_val = phy->ops.write_reg(hw,
660 		} else if (phy->smart_speed == e1000_smart_speed_off) {
661 			ret_val = phy->ops.read_reg(hw,
668 			ret_val = phy->ops.write_reg(hw,
841 	    (hw->phy.type == e1000_phy_igp_3))
864 	if (hw->phy.media_type != e1000_media_type_copper)
890 	if (hw->phy.media_type != e1000_media_type_copper) {
977 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1156 	if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1157 		/* allow time for SFP cage time to power up phy */
1160 		ret_val = hw->phy.ops.reset(hw);
1166 	switch (hw->phy.type) {
1206 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1243 		/* sgmii mode lets the phy handle forcing speed/duplex */
1324 		switch (hw->phy.media_type) {
1441 	struct e1000_phy_info *phy = &hw->phy;
1444 	if (!(phy->ops.check_reset_block))
1448 	if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1513 	if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1704 	ret_val = hw->phy.ops.acquire(hw);
1709 	 * We config the phy address in MDICNFG register now. Same bits
1714 	mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1719 	hw->phy.ops.release(hw);
1741 	ret_val = hw->phy.ops.acquire(hw);
1746 	 * We config the phy address in MDICNFG register now. Same bits
1751 	mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1756 	hw->phy.ops.release(hw);