Lines Matching refs:TDC_BASE_ADDR
35 #define TDC_BASE_ADDR 0X00400000
37 #define TDC_PAGE_HANDLE (TDC_BASE_ADDR + 0x8)
38 #define TDC_TDR_CFG (TDC_BASE_ADDR + 0x20)
39 #define TDC_TDR_HEAD (TDC_BASE_ADDR + 0x28)
40 #define TDC_TDR_PRE_HEAD (TDC_BASE_ADDR + 0x30)
41 #define TDC_TDR_KICK (TDC_BASE_ADDR + 0x38)
42 #define TDC_INT_MASK (TDC_BASE_ADDR + 0x40)
43 #define TDC_STAT (TDC_BASE_ADDR + 0x48)
44 #define TDC_MBH (TDC_BASE_ADDR + 0x50)
45 #define TDC_MBL (TDC_BASE_ADDR + 0x58)
46 #define TDC_BYTE_CNT (TDC_BASE_ADDR + 0x80)
47 #define TDC_TDR_QLEN (TDC_BASE_ADDR + 0x88)
48 #define TDC_RTAB_PTR (TDC_BASE_ADDR + 0x90)
49 #define TDC_DROP_CNT (TDC_BASE_ADDR + 0x98)
50 #define TDC_LAST_PKT_RBUF_PTRS (TDC_BASE_ADDR + 0xA8)
51 #define TDC_PREF_CMD (TDC_BASE_ADDR + 0x100)
52 #define TDC_PREF_DATA (TDC_BASE_ADDR + 0x108)
53 #define TDC_PREF_PAR_DATA (TDC_BASE_ADDR + 0x110)
54 #define TDC_REORD_BUF_CMD (TDC_BASE_ADDR + 0x120)
55 #define TDC_REORD_BUF_DATA (TDC_BASE_ADDR + 0x128)
56 #define TDC_REORD_BUF_ECC_DATA (TDC_BASE_ADDR + 0x130)
57 #define TDC_REORD_TBL_CMD (TDC_BASE_ADDR + 0x140)
58 #define TDC_REORD_TBL_DATA_LO (TDC_BASE_ADDR + 0x148)
59 #define TDC_REORD_TBL_DATA_HI (TDC_BASE_ADDR + 0x150)
60 #define TDC_PREF_PAR_LOG (TDC_BASE_ADDR + 0x200)
61 #define TDC_REORD_BUF_ECC_LOG (TDC_BASE_ADDR + 0x208)
62 #define TDC_REORD_TBL_PAR_LOG (TDC_BASE_ADDR + 0x210)
63 #define TDC_FIFO_ERR_MASK (TDC_BASE_ADDR + 0x220)
64 #define TDC_FIFO_ERR_STAT (TDC_BASE_ADDR + 0x228)
65 #define TDC_FIFO_ERR_INT_DBG (TDC_BASE_ADDR + 0x230)
66 #define TDC_STAT_INT_DBG (TDC_BASE_ADDR + 0x240)
67 #define TDC_PKT_REQ_TID_TAG (TDC_BASE_ADDR + 0x250)
68 #define TDC_SOP_PREF_DESC_LOG (TDC_BASE_ADDR + 0x260)
69 #define TDC_PREF_DESC_LOG (TDC_BASE_ADDR + 0x268)
70 #define TDC_PEU_TXN_LOG (TDC_BASE_ADDR + 0x270)
71 #define TDC_DBG_TRAINING_VEC (TDC_BASE_ADDR + 0x300)
72 #define TDC_DBG_GRP_SEL (TDC_BASE_ADDR + 0x308)