io/hxge/hxge_rdc_hw.h

85  * Description: Logical page handle specifying upper bits of 64-bit
105 	} bits;
130  *     RdcStat ldf1 error bits remain set.
158 	} bits;
191 	} bits;
201  * undefined if the last entry is outside of the page (if bits 43:18
202  * of the address of the last entry are different from bits 43:18 of
217  *     entries in the ring have this as their upper address bits.
242 	} bits;
250  * individual packet buffer sizes. The VLD bits of the three block
251  * sizes have to be set to 1 in normal operations. These bits may be
301 	} bits;
331 	} bits;
354 	} bits;
361  * Description: Lower bits of the RBR head pointer. Software programs
362  * the upper bits, specified in rdcRbrConfigA.staddrBase.
382 	} bits;
427 	} bits;
462 	} bits;
486 	} bits;
493  * Description: Lower bits of the RCR tail pointer. Software programs
494  * the upper bits, specified in rdcRcrConfigA.staddrBase.
514 	} bits;
541 	} bits;
568 	} bits;
576  * bits are used to keep track of normal DMA operations, while the
577  * remaining bits are primarily used to detect error conditions.
646 	} bits;
748 	} bits;
772 	} bits;
813 	} bits;
835 	} bits;
844  * triggers the access. For writes, software writes the 32 bits of
854  *     enable writing of parity bits 1=enabled, 0=disabled
878 	} bits;
887  *     For writes, parity bits is written into prefetch buffer. For
888  *     reads, parity bits read from the prefetch buffer.
904 	} bits;
913  * the access. For writes, software writes the 64 bits of data to the
922  *     enable writing of parity bits 1=enabled, 0=disabled
946 	} bits;
968 	} bits;
992 	} bits;
1001  * triggers the access. For writes, software writes the 128 bits of
1011  *     enable writing of ECC bits 1=enabled, 0=disabled
1032 	} bits;
1039  * Description: Lower 64 bits read or written to the Rx Ctl FIFO. See
1055 	} bits;
1062  * Description: Upper 64 bits read or written to the Rx Ctl FIFO. See
1078 	} bits;
1085  * Description: 16 bits ECC data read or written to the Rx Ctl FIFO.
1107 	} bits;
1116  * triggers the access. For writes, software writes the 128 bits of
1126  *     enable writing of ECC bits 1=enabled, 0=disabled
1147 	} bits;
1154  * Description: Lower 64 bits read or written to the Rx Data FIFO.
1170 	} bits;
1177  * Description: Upper 64 bits read or written to the Rx Data FIFO.
1193 	} bits;
1200  * Description: 16 bits ECC data read or written to the Rx Data FIFO.
1222 	} bits;
1230  * Debug RDC control and status register bits to check if interrupt
1285 	} bits;
1310 	} bits;
1335 	} bits;
1346  *     Address of ECC error for upper 64 bits Writing a 1 to
1349  *     Address of ECC error for lower 64 bits Writing a 1 to
1352  *     ECC syndrome for upper 64 bits Writing a 1 to
1355  *     ECC syndrome for lower 64 bits Writing a 1 to
1381 	} bits;
1392  *     Address of ECC error for upper 64 bits Writing a 1 to
1395  *     Address of ECC error for lower 64 bits Writing a 1 to
1398  *     ECC syndrome for upper 64 bits Writing a 1 to
1401  *     ECC syndrome for lower 64 bits Writing a 1 to
1427 	} bits;
1465 	} bits;
1474  * the two error bits point to one of the memory. Each entry in the
1476  * The two error bits point to each half of the entry.
1511 	} bits;
1544 	} bits;
1573 	} bits;
1613 	} bits;
1641 	} bits;