Lines Matching defs:bits
207 } bits;
310 } bits;
338 } bits;
369 } bits;
379 * bits and PIO BAR0 handles the lower address bits.
407 } bits;
427 } bits;
437 * address bits and MSIX BAR0 handles the lower address bits.
464 } bits;
484 } bits;
520 } bits;
540 } bits;
559 } bits;
581 } bits;
610 } bits;
631 } bits;
659 } bits;
704 } bits;
748 } bits;
757 * Mask and Pending bits available
787 } bits;
808 } bits;
827 } bits;
838 * vectors, bits [4:0] may be replaced with msiVector[4:0] bits
855 } bits;
864 * per vector MSI Mask bits
874 } bits;
883 * per vector MSI Pending bits
893 } bits;
927 } bits;
950 } bits;
975 } bits;
1011 } bits;
1061 } bits;
1150 } bits;
1196 } bits;
1258 } bits;
1285 } bits;
1320 } bits;
1347 } bits;
1369 } bits;
1388 } bits;
1420 } bits;
1450 } bits;
1501 } bits;
1529 } bits;
1566 } bits;
1591 } bits;
1611 } bits;
1646 } bits;
1700 } bits;
1722 } bits;
1744 } bits;
1766 } bits;
1790 } bits;
1797 * Description: This register returns bits [31:0] of the PIPE core's
1803 * in spec. except for the clock bits which are hardwired to
1809 * multiplied by 16. lane0 is bits[15:0], lane1 is bits[31:16],
1810 * lane2 is bits[47:32], lane3 is bits[63:48], lane4 is
1811 * bits[79:64], lane5 is bits[95:80], lane6 is bits[111:96],
1812 * lane7 is bits[127:112].
1817 * lane0 is bits[15:0], which is gbtDebug0[15:0] lane1 is
1818 * bits[31:16], which is gbtDebug0[31:16]
1844 } bits;
1851 * Description: This register returns bits [63:32] of the PIPE core's
1857 * in spec. except for the clock bits which are hardwired to
1868 * lane2 is bits[47:32], which is gbtDebug1[15:0] lane3 is
1869 * bits[63:48], which is gbtDebug1[31:16]
1895 } bits;
1902 * Description: This register returns bits [95:64] of the PIPE core's
1908 * in spec. except for the clock bits which are hardwired to
1919 * lane4 is bits[79:64], which is gbtDebug2[15:0] lane5 is
1920 * bits[95:80], which is gbtDebug2[31:16]
1946 } bits;
1953 * Description: This register returns bits [127:96] of the PIPE
1959 * in spec. except for the clock bits which are hardwired to
1970 * lane6 is bits[111:96], which is gbtDebug3[15:0] lane7 is
1971 * bits[127:112], which is gbtDebug3[31:16]
1997 } bits;
2004 * Description: This register returns bits [31:0] of the PIPE core's
2011 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2012 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2013 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2054 } bits;
2061 * Description: This register returns bits [63:32] of the PIPE core's
2068 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2069 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2070 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2075 * lane2 is bits[47:32], which is pipeDebug1[15:0] lane3 is
2076 * bits[63:48], which is pipeDebug1[31:16]
2111 } bits;
2122 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2123 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2124 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2129 * lane4 is bits[79:64], which is pipeDebug2[15:0] lane5 is
2130 * bits[95:80], which is pipeDebug2[31:16]
2165 } bits;
2172 * Description: This register returns bits [127:96] of the PIPE
2179 * is bits[15:0], lane1 is bits[31:16], lane2 is bits[47:32],
2180 * lane3 is bits[63:48], lane4 is bits[79:64], lane5 is
2181 * bits[95:80], lane6 is bits[111:96], lane7 is bits[127:112].
2186 * lane6 is bits[111:96], which is pipeDebug3[15:0] lane7 is
2187 * bits[127:112], which is pipeDebug3[31:16]
2222 } bits;
2248 } bits;
2303 } bits;
2358 } bits;
2414 } bits;
2454 } bits;
2494 } bits;
2527 } bits;
2546 } bits;
2565 } bits;
2584 } bits;
2603 } bits;
2653 } bits;
2669 } bits;
2717 } bits;
2772 } bits;
2816 } bits;
2851 } bits;
2893 } bits;
2918 } bits;
2940 * software. Writing a '1' to any of these bits generates a single
2965 * bits. Clears to 0, writing 0 has no effect.
3064 } bits;
3091 } bits;
3117 } bits;
3142 } bits;
3162 } bits;
3232 } bits;
3287 } bits;
3309 * The EEPROM is 1M x 16 bits or 2M bytes. The read address in bits
3311 * While accessing through these registers, the lower 2 bits of the
3320 * locations 0 & 1 which are 16 bits each, and a read to addr=4,5,6,7
3321 * will return data from EPC locations 2,3 which are 16 bits each.
3342 * bits in cipStatus register) is stuck at a non-zero state.
3383 } bits;
3404 } bits;
3436 } bits;
3460 } bits;
3507 } bits;
3534 } bits;
3543 * Host is allowed 8 bits read/write access to this register ; To do
3545 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3606 } bits;
3614 * Host is allowed a 32 bits read/write access to this register ; To
3617 * bits read/write access to this register ; To do the same, it
3620 * All references to the mail box control bits in this register
3638 } bits;
3647 * Host is allowed 8 bits read/write access to this register ; To do
3649 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3652 * All references to the mail box control bits in this register
3695 } bits;
3704 * Host is allowed 8 bits read/write access to this register ; To do
3706 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3767 } bits;
3775 * Host is allowed a 32 bits read/write access to this register ; To
3778 * bits read/write access to this register ; To do the same, it
3781 * All references to the mail box control bits in this register
3798 } bits;
3807 * Host is allowed 8 bits read/write access to this register ; To do
3809 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3812 * All references to the mail box control bits in this register
3855 } bits;
3864 * Host is allowed 8 bits read/write access to this register ; To do
3866 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
3927 } bits;
3935 * references to the mail box control bits in this register refer to
3937 * Host is allowed a 32 bits read/write access to this register ; To
3940 * bits read/write access to this register ; To do the same, it
3959 } bits;
3968 * Host is allowed 8 bits read/write access to this register ; To do
3970 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
3973 * All references to the mail box control bits in this register
4016 } bits;
4025 * Host is allowed 8 bits read/write access to this register ; To do
4027 * hostDataBus[7:0], and assert hostBen[0], SPI is allowed 8 bits
4088 } bits;
4096 * Host is allowed a 32 bits read/write access to this register ; To
4099 * bits read/write access to this register ; To do the same, it
4102 * All references to the mail box control bits in this register
4119 } bits;
4128 * Host is allowed 8 bits read/write access to this register ; To do
4130 * hostDataBus[23:16], and assert hostBen[2], SPI is allowed 8 bits
4133 * All references to the mail box control bits in this register
4176 } bits;
4209 } bits;
4264 } bits;
4274 * selected by mem0Sel bits from mem0Ctrl This data is written to
4297 } bits;
4307 * selected by mem0Sel bits from mem0Ctrl This data is written to
4322 } bits;
4332 * selected by mem0Sel bits from mem0Ctrl This data is written to
4348 } bits;
4358 * selected by mem0Sel bits from mem0Ctrl This data is written to
4373 } bits;
4382 * parity mask bits for the memory selected by mem0Sel bits from
4383 * mem0Ctrl to inject parity error These bits serve two purposes
4405 } bits;
4462 } bits;
4472 * selected by mem1Sel bits from mem1Ctrl This data is written to
4495 } bits;
4505 * selected by mem1Sel bits from mem1Ctrl This data is written to
4511 * tdcPeuTlp0[or rdcPeuTlp1]_addr[63:32] high address bits.
4521 } bits;
4531 * selected by mem1Sel bits from mem1Ctrl This data is written to
4537 * tdcPeuTlp0[or rdcPeuTlp1]_addr[31:0] low address bits.
4547 } bits;
4557 * selected by mem1Sel bits from mem1Ctrl This data is written to
4573 } bits;
4582 * parity mask bits for the memory selected by mem1Sel bits from
4583 * mem1Ctrl to inject parity error These bits serve two purposes
4605 } bits;
4633 } bits;
4673 } bits;
4719 } bits;
4783 } bits;
4793 * bits define the BAR register number whose mask value has to be
4798 * Forms 64 bit PIO BAR. BAR1 handles the upper address bits BAR0
4799 * handles the lower address bits BAR3, BAR2 : Forms 64 bit MSIX BAR
4800 * BAR3 handles the upper address bits BAR2 handles the lower address
4801 * bits BAR5, BAR4 : Not used and so disabled. Hence, user writes
4818 } bits;
4826 * Core PCI Config registers The lower 3 bits of cipMaskCfg register
4847 } bits;
4867 } bits;
4887 } bits;
4900 * Partity Error bits: These bits log the very first parity error
4903 * Access Error bits: These bits log the very first error that
4906 * These bits can be set by writing a '1' to the corresponding
4909 * When these bits are set and the device error status interrupt is
4993 } bits;
5072 } bits;
5079 * Description: Mirror bits for Parity error generation in the PEU
5083 * of the status bits is controlled by how the Parity Error Status
5084 * Register is cleared. These bits cannot be cleared by writing 0 to
5129 } bits;
5151 } bits;
5173 } bits;
5195 } bits;
5217 } bits;
5239 } bits;
5261 } bits;
5283 } bits;
5305 } bits;
5327 } bits;
5349 } bits;
5376 } bits;
5403 } bits;
5430 } bits;
5457 } bits;
5478 } bits;
5488 * Device Error Status bits [31:16] feed LDSV0.devErr0 Device Error
5489 * Status bits [15:0] feed LDSV1.devErr1
5533 } bits;
5573 } bits;
5594 } bits;
5607 * Flag0 bits for Network MAC
5608 * Flag0 bits for Virtual MAC
5609 * Flag0 bits for Tx DMA channels 3-0
5610 * Flag0 bits for Rx DMA channels 3-0
5646 } bits;
5655 * Flag1 bits for Network MAC
5656 * Flag1 bits for Tx DMA channels 3-0
5657 * Flag1 bits for Rx DMA channels 3-0
5685 } bits;
5709 } bits;
5734 } bits;
5755 } bits;