Lines Matching refs:bits
106 cfg.bits.reset = 1;
113 cfg.bits.enable = 1;
119 * Sets reset bit only (Hardware will reset all the RW bits but
120 * leave the RO bits alone.
123 cfg.bits.reset = 1;
130 cfg.bits.enable = 1;
137 cfg.bits.enable = 0;
152 cs.bits.mb = 1;
300 ml.bits.mbaddr = ((*mbox_addr & TDC_MBL_MASK) >> TDC_MBL_SHIFT);
302 mh.bits.mbaddr = ((*mbox_addr >> TDC_MBH_ADDR_SHIFT) &
341 desc_p->bits.sop = 1;
342 desc_p->bits.mark = mark;
343 desc_p->bits.num_ptr = ngathers;
346 desc_p->bits.tr_len, transfer_len));
348 desc_p->bits.tr_len = transfer_len;
349 desc_p->bits.sad = dma_ioaddr >> 32;
350 desc_p->bits.sad_l = dma_ioaddr & 0xffffffff;
354 desc_p->bits.tr_len, transfer_len));
420 sad = desp->bits.sad;
421 sad = (sad << 32) | desp->bits.sad_l;
422 xfer_len = desp->bits.tr_len;
426 desp->value, sad, desp->bits.tr_len, xfer_len,
427 desp->bits.num_ptr, desp->bits.mark, desp->bits.sop));
450 if (txcs.bits.qst) {
459 "cleared to 0 txcs.bits 0x%llx", txcs.value));
475 if (txcs.bits.qst) {
484 "set to 1 txcs.bits 0x%llx", txcs.value));