io/hxge/hpi_rxdma.c

55 	page_hdl.bits.handle = (uint32_t)page_handle;
71 	while ((count--) && (cfg.bits.qst == 0)) {
76 	if (cfg.bits.qst == 0)
100 		cfg.bits.enable = 1;
106 		while ((count--) && (cfg.bits.qst == 1)) {
110 		if (cfg.bits.qst == 1) {
117 		cfg.bits.enable = 0;
133 		cfg.bits.reset = 1;
138 		while ((count--) && (cfg.bits.qst == 0)) {
191 		rcr_cfgb.bits.timeout = (uint8_t)param;
192 		rcr_cfgb.bits.entout = 1;
196 		rcr_cfgb.bits.pthres = param;
200 		rcr_cfgb.bits.entout = 0;
257 		cfg1.bits.mbaddr_h = (rdc_desc_cfg->mbox_addr >> 32) & 0xfff;
258 		cfg2.bits.mbaddr_l = ((rdc_desc_cfg->mbox_addr &
272 		cfg2.bits.full_hdr = 1;
275 		cfg2.bits.offset = rdc_desc_cfg->offset;
277 		cfg2.bits.offset = SW_OFFSET_NO_OFFSET;
284 	/* The remaining 20 bits in the DMA address form the handle */
285 	page_handle.bits.handle = (rdc_desc_cfg->rbr_addr >> 44) && 0xfffff;
300 	 * The lower 6 bits are hardcoded to 0 and the higher 10 bits are
303 	cfga.bits.len = rdc_desc_cfg->rbr_len >> 6;
306 	    cfga.value, cfga.bits.len, rdc_desc_cfg->rbr_len));
313 		cfgb.bits.bksize = RBR_BKSIZE_4K;
315 		cfgb.bits.bksize = RBR_BKSIZE_8K;
328 			cfgb.bits.bufsz0 = RBR_BUFSZ0_256B;
330 			cfgb.bits.bufsz0 = RBR_BUFSZ0_512B;
332 			cfgb.bits.bufsz0 = RBR_BUFSZ0_1K;
340 		cfgb.bits.vld0 = 1;
342 		cfgb.bits.vld0 = 0;
350 			cfgb.bits.bufsz1 = RBR_BUFSZ1_1K;
352 			cfgb.bits.bufsz1 = RBR_BUFSZ1_2K;
360 		cfgb.bits.vld1 = 1;
362 		cfgb.bits.vld1 = 0;
370 			cfgb.bits.bufsz2 = RBR_BUFSZ2_2K;
372 			cfgb.bits.bufsz2 = RBR_BUFSZ2_4K;
380 		cfgb.bits.vld2 = 1;
382 		cfgb.bits.vld2 = 0;
404 	rcr_cfga.bits.len = rdc_desc_cfg->rcr_len >> 5;
411 			rcr_cfgb.bits.timeout = rdc_desc_cfg->rcr_timeout;
412 			rcr_cfgb.bits.entout = 1;
418 			rcr_cfgb.bits.entout = 0;
421 		rcr_cfgb.bits.entout = 0;
426 		rcr_cfgb.bits.pthres = rdc_desc_cfg->rcr_threshold;
431 		rcr_cfgb.bits.pthres = 1;
475 	clk_div.bits.count = count;
515 	*rcr_qlen =  stats.bits.qlen;
518 	    rdc, *rcr_qlen, stats.bits.qlen));
534 	cs.bits.rbr_empty = 1;