fca/oce/oce_intr.c

39  * dev - software handle to the device
44 oce_setup_intr(struct oce_dev *dev)
55 	ret = ddi_intr_get_supported_types(dev->dip, &intr_types);
57 		oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
64 		dev->intr_type = DDI_INTR_TYPE_MSIX;
66 		nreqd = dev->rx_rings + 1;
69 		dev->intr_type = DDI_INTR_TYPE_FIXED;
74 	ret = ddi_intr_get_nintrs(dev->dip, dev->intr_type, &nsupported);
76 		oce_log(dev, CE_WARN, MOD_CONFIG,
82 	ret = ddi_intr_get_navail(dev->dip, dev->intr_type, &navail);
84 		oce_log(dev, CE_WARN, MOD_CONFIG,
100 	dev->hsize  = nreqd *  sizeof (ddi_intr_handle_t);
101 	dev->htable = kmem_zalloc(dev->hsize,  KM_NOSLEEP);
103 	if (dev->htable == NULL)
108 	ret = ddi_intr_alloc(dev->dip, dev->htable, dev->intr_type,
115 	dev->num_vectors = nallocd;
125 	ret = ddi_intr_get_pri(dev->htable[0], &dev->intr_pri);
131 	(void) ddi_intr_get_cap(dev->htable[0], &dev->intr_cap);
134 		dev->rx_rings = nallocd - 1;
136 		dev->rx_rings = 1;
142 	(void) oce_teardown_intr(dev);
143 	if ((dev->intr_type == DDI_INTR_TYPE_MSIX) &&
146 		oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
156  * dev - software handle to the device
161 oce_teardown_intr(struct oce_dev *dev)
166 	for (i = 0; i < dev->num_vectors; i++) {
167 		(void) ddi_intr_free(dev->htable[i]);
171 	kmem_free(dev->htable, dev->hsize);
172 	dev->htable = NULL;
180  * dev - software handle to the device
185 oce_setup_handlers(struct oce_dev *dev)
189 	for (i = 0; i < dev->num_vectors; i++) {
190 		ret = ddi_intr_add_handler(dev->htable[i], oce_isr,
191 		    (caddr_t)dev->eq[i], NULL);
193 			oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
196 				(void) ddi_intr_remove_handler(dev->htable[i]);
207  * dev - software handle to the device
212 oce_remove_handler(struct oce_dev *dev)
215 	for (nvec = 0; nvec < dev->num_vectors; nvec++) {
216 		(void) ddi_intr_remove_handler(dev->htable[nvec]);
221 oce_chip_ei(struct oce_dev *dev)
225 	reg =  OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
226 	if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
227 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
230 	OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
231 	if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
232 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
239  * dev - software handle to the device
244 oce_ei(struct oce_dev *dev)
249 	if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) {
250 		(void) ddi_intr_block_enable(dev->htable, dev->num_vectors);
253 		for (i = 0; i < dev->num_vectors; i++) {
254 			ret = ddi_intr_enable(dev->htable[i]);
257 					(void) ddi_intr_disable(dev->htable[i]);
262 	oce_chip_ei(dev);
266 oce_chip_di(struct oce_dev *dev)
270 	reg =  OCE_CFG_READ32(dev, PCICFG_INTR_CTRL);
271 	if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
272 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
275 	OCE_CFG_WRITE32(dev, PCICFG_INTR_CTRL, reg);
276 	if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
277 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
284  * dev - software handle to the device
289 oce_di(struct oce_dev *dev)
294 	oce_chip_di(dev);
295 	if (dev->intr_cap & DDI_INTR_FLAG_BLOCK) {
296 		(void) ddi_intr_block_disable(dev->htable, dev->num_vectors);
298 		for (i = 0; i < dev->num_vectors; i++) {
299 			ret = ddi_intr_disable(dev->htable[i]);
301 				oce_log(dev, CE_WARN, MOD_CONFIG,
324 	struct oce_dev  *dev;
330 	dev = eq->parent;
340 			oce_log(dev, CE_WARN, MOD_ISR,
347 		cq = dev->cq[cq_id];
360 	oce_arm_eq(dev, eq->eq_id, num_eqe, B_TRUE, B_TRUE);