fca/oce/oce_hw.c

43 extern int oce_destroy_q(struct oce_dev *dev, struct oce_mbx *mbx,
47 oce_map_regs(struct oce_dev *dev)
52 	ASSERT(NULL != dev);
53 	ASSERT(NULL != dev->dip);
56 	ret = ddi_dev_nregs(dev->dip, &dev->num_bars);
58 		oce_log(dev, CE_WARN, MOD_CONFIG,
65 	ret = ddi_dev_regsize(dev->dip, OCE_DEV_CFG_BAR, &bar_size);
67 		oce_log(dev, CE_WARN, MOD_CONFIG,
73 	ret = ddi_regs_map_setup(dev->dip, OCE_DEV_CFG_BAR, &dev->dev_cfg_addr,
74 	    0, bar_size, &reg_accattr, &dev->dev_cfg_handle);
77 		oce_log(dev, CE_WARN, MOD_CONFIG,
84 	ret = ddi_dev_regsize(dev->dip, OCE_PCI_CSR_BAR, &bar_size);
87 		oce_log(dev, CE_WARN, MOD_CONFIG,
93 	ret = ddi_regs_map_setup(dev->dip, OCE_PCI_CSR_BAR, &dev->csr_addr,
94 	    0, bar_size, &reg_accattr, &dev->csr_handle);
96 		oce_log(dev, CE_WARN, MOD_CONFIG,
99 		ddi_regs_map_free(&dev->dev_cfg_handle);
104 	ret = ddi_dev_regsize(dev->dip, OCE_PCI_DB_BAR, &bar_size);
106 		oce_log(dev, CE_WARN, MOD_CONFIG,
109 		ddi_regs_map_free(&dev->csr_handle);
110 		ddi_regs_map_free(&dev->dev_cfg_handle);
114 	ret = ddi_regs_map_setup(dev->dip, OCE_PCI_DB_BAR, &dev->db_addr,
115 	    0, 0, &reg_accattr, &dev->db_handle);
117 		oce_log(dev, CE_WARN, MOD_CONFIG,
119 		ddi_regs_map_free(&dev->csr_handle);
120 		ddi_regs_map_free(&dev->dev_cfg_handle);
126 oce_unmap_regs(struct oce_dev *dev)
129 	ASSERT(NULL != dev);
130 	ASSERT(NULL != dev->dip);
132 	ddi_regs_map_free(&dev->db_handle);
133 	ddi_regs_map_free(&dev->csr_handle);
134 	ddi_regs_map_free(&dev->dev_cfg_handle);
145  * dev - handle to device private data structure
149 oce_pci_init(struct oce_dev *dev)
153 	ret = pci_config_setup(dev->dip, &dev->pci_cfg_handle);
158 	ret = oce_map_regs(dev);
161 		pci_config_teardown(&dev->pci_cfg_handle);
164 	dev->fn =  OCE_PCI_FUNC(dev);
165 	if (oce_fm_check_acc_handle(dev, dev->dev_cfg_handle) != DDI_FM_OK) {
166 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
170 		oce_pci_fini(dev);
181  * dev - handle to device private data
184 oce_pci_fini(struct oce_dev *dev)
186 	oce_unmap_regs(dev);
187 	pci_config_teardown(&dev->pci_cfg_handle);
194  * dev - software handle to the device
198 oce_is_reset_pci(struct oce_dev *dev)
202 	ASSERT(dev != NULL);
203 	ASSERT(dev->dip != NULL);
206 	post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
217  * dev - software handle to the device
221 oce_pci_soft_reset(struct oce_dev *dev)
229 	ASSERT(dev != NULL);
232 	soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
234 	OCE_CFG_WRITE32(dev, PCICFG_SOFT_RESET, soft_rst.dw0);
244 		soft_rst.dw0 = OCE_CFG_READ32(dev, PCICFG_SOFT_RESET);
250 		oce_log(dev, CE_WARN, MOD_CONFIG,
257 	return (oce_POST(dev));
262  * dev - software handle to the device
266 oce_POST(struct oce_dev *dev)
273 	post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
274 	if (oce_fm_check_acc_handle(dev, dev->csr_handle) != DDI_FM_OK) {
275 		ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
281 		OCE_CSR_WRITE32(dev, MPU_EP_SEMAPHORE, post_status.dw0);
282 		if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
284 			ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
297 		post_status.dw0 = OCE_CSR_READ32(dev, MPU_EP_SEMAPHORE);
298 		if (oce_fm_check_acc_handle(dev, dev->csr_handle) !=
300 			ddi_fm_service_impact(dev->dip, DDI_SERVICE_DEGRADED);
304 			oce_log(dev, CE_WARN, MOD_CONFIG,
336 oce_create_nw_interface(struct oce_dev *dev)
342 	if (dev->rss_enable) {
348 	ret = oce_if_create(dev, capab_flags, capab_en_flags,
349 	    0, &dev->mac_addr[0], (uint32_t *)&dev->if_id);
351 		oce_log(dev, CE_WARN, MOD_CONFIG,
355 	atomic_inc_32(&dev->nifs);
357 	dev->if_cap_flags = capab_en_flags;
360 	ret = oce_config_vlan(dev, (uint8_t)dev->if_id, NULL, 0,
363 		oce_log(dev, CE_WARN, MOD_CONFIG,
365 		oce_delete_nw_interface(dev);
371 	ret = oce_set_flow_control(dev, dev->flow_control);
373 		oce_log(dev, CE_NOTE, MOD_CONFIG,
376 	ret = oce_set_promiscuous(dev, dev->promisc);
379 		oce_log(dev, CE_NOTE, MOD_CONFIG,
387 oce_delete_nw_interface(struct oce_dev *dev) {
390 	if (dev->nifs > 0) {
391 		(void) oce_if_del(dev, dev->if_id);
392 		atomic_dec_32(&dev->nifs);
397 oce_create_itbl(struct oce_dev *dev, char *itbl)
400 	struct oce_rq **rss_queuep = &dev->rq[1];
401 	int nrss  = dev->nrqs - 1;
409 oce_setup_adapter(struct oce_dev *dev)
416 	oce_chip_di(dev);
418 	ret = oce_create_nw_interface(dev);
422 	ret = oce_create_queues(dev);
424 		oce_delete_nw_interface(dev);
427 	if (dev->rss_enable) {
428 		(void) oce_create_itbl(dev, itbl);
430 		ret = oce_config_rss(dev, dev->if_id, hkey, itbl, OCE_ITBL_SIZE,
433 			oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
435 			oce_delete_queues(dev);
436 			oce_delete_nw_interface(dev);
440 	ret = oce_setup_handlers(dev);
442 		oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
444 		oce_delete_queues(dev);
445 		oce_delete_nw_interface(dev);
452 oce_unsetup_adapter(struct oce_dev *dev)
454 	oce_remove_handler(dev);
455 	if (dev->rss_enable) {
460 		ret = oce_config_rss(dev, dev->if_id, hkey, itbl, OCE_ITBL_SIZE,
464 			oce_log(dev, CE_NOTE, MOD_CONFIG, "%s",
468 	oce_delete_queues(dev);
469 	oce_delete_nw_interface(dev);
473 oce_hw_init(struct oce_dev *dev)
478 	ret = oce_POST(dev);
480 		oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
486 	dev->bmbx = oce_alloc_dma_buffer(dev,
488 	if (dev->bmbx == NULL) {
489 		oce_log(dev, CE_WARN, MOD_CONFIG,
495 	ret = oce_reset_fun(dev);
497 		oce_log(dev, CE_WARN, MOD_CONFIG, "%s",
503 	ret = oce_mbox_init(dev);
505 		oce_log(dev, CE_WARN, MOD_CONFIG,
511 	ret = oce_get_fw_version(dev);
513 		oce_log(dev, CE_WARN, MOD_CONFIG,
519 	ret = oce_get_fw_config(dev);
521 		oce_log(dev, CE_WARN, MOD_CONFIG,
527 	ret = oce_read_mac_addr(dev, 0, 1,
530 		oce_log(dev, CE_WARN, MOD_CONFIG,
534 	bcopy(&mac_addr.mac_addr[0], &dev->mac_addr[0], ETHERADDRL);
537 	oce_hw_fini(dev);
541 oce_hw_fini(struct oce_dev *dev)
543 	if (dev->bmbx != NULL) {
544 		oce_free_dma_buffer(dev, dev->bmbx);
545 		dev->bmbx = NULL;