common/io/ecpp.c

1121 	    "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
1220 	ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
1560 		rg.dcr = DCR_READ(pp);
1564 		ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",
1565 		    rg.dsr, rg.dcr);
1569 		rg.dcr |= ECPP_SETREGS_DCR_MASK;
2183 		uint8_t dcr;
2194 		if ((rg->dcr & ECPP_SETREGS_DCR_MASK) !=
2200 		/* get the old dcr */
2201 		dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
2202 		/* get the new dcr */
2203 		dcr = (dcr & ECPP_SETREGS_DCR_MASK) |
2204 		    (rg->dcr & ~ECPP_SETREGS_DCR_MASK);
2205 		DCR_WRITE(pp, dcr);
2206 		ecpp_error(pp->dip, "ECPPIOC_SETREGS:dcr=%x\n", dcr);
2548 	uint8_t		ecr, dcr;
2618 			dcr = DCR_READ(pp);
2619 			dcr &= ~(ECPP_REV_DIR | ECPP_INTR_EN);
2620 			DCR_WRITE(pp, dcr);
2859 	ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n",
3227 	    "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3239 	    "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3287 	ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3377 	uint8_t	dcr;
3379 	dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
3380 	dcr |= ECPP_INTR_EN;
3388 	if (dcr_write(pp, dcr | ECPP_STB) == FAILURE) {
3398 	if (dcr_write(pp, dcr & ~ECPP_STB) == FAILURE) {
3617 	uint8_t		dcr;
3639 		dcr = DCR_READ(pp);
3640 		(void) dcr_write(pp, dcr & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3784 	    "(%d)dcr_write: dcr written =%x, dcr readback =%x\n",
4830  * (manipulations with dcr/ecr are according to ECP Specification)
4864  * (manipulations with dcr/ecr are according to ECP Specification)
5908 	ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5926 	ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",