Lines Matching defs:ecr

1121 	    "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
1220 ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
2548 uint8_t ecr, dcr;
2669 ecr = ECR_READ(pp);
2670 if (!(ecr & ECPP_FIFO_EMPTY)) {
2673 ECR_WRITE(pp, ecr);
2717 "ecpp_start:current_mode=%x,current_phase=%x,ecr=%x,len=%d\n",
2859 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n",
2878 uint8_t ecr;
2929 ecr = ecr_mode[pp->current_mode];
2930 (void) ecr_write(pp, ecr | ECPP_INTR_SRV | ECPP_INTR_MASK);
2939 (void) ecr_write(pp, ecr | ECPP_DMA_ENABLE | ECPP_INTR_MASK);
3227 "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3239 "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3287 ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3808 uint8_t ecr;
3829 ecr = ECR_READ(pp);
3832 (((ecr & ECPP_FIFO_EMPTY) == 0) &&
3836 "ecpp_fifo_timer(%d):FIFO not empty:ecr=%x\n",
3837 pp->ecpp_drain_counter, ecr);
3854 " clearing FIFO,can't wait:ecr=%x\n",
3855 pp->ecpp_drain_counter, ecr);
3858 "ecpp_fifo_timer(%d):FIFO empty:ecr=%x\n",
3859 pp->ecpp_drain_counter, ecr);
3931 (void) ecr_write(pp, (ecr & 0xe0) |
4830 * (manipulations with dcr/ecr are according to ECP Specification)
4864 * (manipulations with dcr/ecr are according to ECP Specification)
5012 ecpp_error(pp->dip, "mode_nego:ECP: failed w/ecr\n");
5031 ecpp_error(pp->dip, "put to TFIFO: failed w/ecr\n");
5689 uint8_t ecr;
5708 ecr = ECR_READ(pp);
5709 if (ecr_write(pp, ecr & ~ECPP_DMA_ENABLE) == FAILURE) {
5714 ecr = ECR_READ(pp);
5716 return (ecr_write(pp, ecr | ECPP_INTR_SRV));
5908 ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5920 ecpp_error(pp->dip, "config chip: failed w/ecr\n");
5926 ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5987 uint8_t ecr;
5990 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
5991 (void) ecr_write(pp, ecr);
6033 uint8_t ecr;
6038 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
6039 (void) ecr_write(pp, ecr);