Lines Matching refs:ret_val
91 s32 ret_val = E1000_SUCCESS;
126 ret_val = e1000_get_phy_id(hw);
130 ret_val = -E1000_ERR_PHY;
135 return (ret_val);
204 s32 ret_val = E1000_SUCCESS;
256 ret_val = -E1000_ERR_CONFIG;
290 return (ret_val);
390 s32 ret_val;
394 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
395 if (ret_val)
398 ret_val = e1000_acquire_nvm_generic(hw);
400 if (ret_val)
404 return (ret_val);
436 s32 ret_val = E1000_SUCCESS;
443 ret_val = -E1000_ERR_SWFW_SYNC;
462 ret_val = -E1000_ERR_SWFW_SYNC;
472 return (ret_val);
513 s32 ret_val;
519 ret_val = e1000_acquire_phy_80003es2lan(hw);
520 if (ret_val)
535 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
536 if (ret_val) {
550 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
553 ret_val = -E1000_ERR_PHY;
560 ret_val = e1000_read_phy_reg_mdic(hw,
566 ret_val = e1000_read_phy_reg_mdic(hw,
573 return (ret_val);
588 s32 ret_val;
594 ret_val = e1000_acquire_phy_80003es2lan(hw);
595 if (ret_val)
610 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
611 if (ret_val) {
625 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
628 ret_val = -E1000_ERR_PHY;
635 ret_val = e1000_write_phy_reg_mdic(hw,
641 ret_val = e1000_write_phy_reg_mdic(hw,
648 return (ret_val);
680 s32 ret_val = E1000_SUCCESS;
696 ret_val = -E1000_ERR_RESET;
701 return (ret_val);
714 s32 ret_val = E1000_SUCCESS;
727 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
728 if (ret_val)
732 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
733 if (ret_val)
738 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);
739 if (ret_val)
747 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
748 if (ret_val)
757 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
759 if (ret_val)
767 ret_val = e1000_phy_reset_dsp_generic(hw);
768 if (ret_val)
773 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
775 if (ret_val)
779 ret_val =
781 if (ret_val)
799 ret_val =
803 return (ret_val);
817 s32 ret_val = E1000_SUCCESS;
825 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
826 if (ret_val)
832 ret_val = E1000_ERR_PHY;
842 return (ret_val);
856 s32 ret_val;
861 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
866 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
871 return (ret_val);
884 s32 ret_val;
892 ret_val = e1000_disable_pcie_master_generic(hw);
893 if (ret_val) {
909 ret_val = e1000_acquire_phy_80003es2lan(hw);
914 ret_val = e1000_get_auto_rd_done_generic(hw);
915 if (ret_val)
923 ret_val = e1000_check_alt_mac_addr_generic(hw);
926 return (ret_val);
940 s32 ret_val;
948 ret_val = mac->ops.id_led_init(hw);
949 if (ret_val) {
968 ret_val = mac->ops.setup_link(hw);
1006 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1010 if (!ret_val) {
1024 return (ret_val);
1076 s32 ret_val;
1083 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1085 if (ret_val)
1092 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1094 if (ret_val)
1105 ret_val =
1107 if (ret_val)
1136 ret_val =
1138 if (ret_val)
1142 ret_val = hw->phy.ops.commit(hw);
1143 if (ret_val) {
1151 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1155 if (ret_val)
1158 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1161 if (ret_val)
1165 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1168 if (ret_val)
1171 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1172 if (ret_val)
1176 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1177 if (ret_val)
1184 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1185 if (ret_val)
1196 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1198 if (ret_val)
1200 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1203 if (ret_val)
1207 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1210 if (ret_val)
1218 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1219 if (ret_val)
1223 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);
1224 if (ret_val)
1228 return (ret_val);
1242 s32 ret_val;
1257 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1259 if (ret_val)
1261 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1263 if (ret_val)
1266 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1268 if (ret_val)
1270 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1273 if (ret_val)
1276 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1279 if (ret_val)
1282 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1283 if (ret_val)
1286 ret_val = e1000_setup_copper_link_generic(hw);
1289 return (ret_val);
1303 s32 ret_val = E1000_SUCCESS;
1311 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1314 if (ret_val)
1318 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1320 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1324 return (ret_val);
1338 s32 ret_val = E1000_SUCCESS;
1346 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1349 if (ret_val)
1360 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1362 if (ret_val)
1365 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1367 if (ret_val)
1377 ret_val =
1381 return (ret_val);
1394 s32 ret_val = E1000_SUCCESS;
1402 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1405 if (ret_val)
1416 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1418 if (ret_val)
1421 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1423 if (ret_val)
1429 ret_val =
1433 return (ret_val);
1450 s32 ret_val = E1000_SUCCESS;
1454 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1455 if (ret_val)
1470 return (ret_val);
1487 s32 ret_val = E1000_SUCCESS;
1491 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1492 if (ret_val)
1504 return (ret_val);
1514 s32 ret_val = E1000_SUCCESS;
1522 ret_val = e1000_check_alt_mac_addr_generic(hw);
1523 if (ret_val)
1526 ret_val = e1000_read_mac_addr_generic(hw);
1529 return (ret_val);