Lines Matching defs:cmac
95 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
97 (void) t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
101 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
103 (void) t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
109 static int pm3393_reset(struct cmac *cmac)
122 static int pm3393_interrupt_enable(struct cmac *cmac)
131 (void) pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
132 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
133 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
134 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
137 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
138 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
139 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
140 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
142 (void) pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
143 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
144 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
145 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
146 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
147 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
148 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
149 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
150 (void) pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
155 (void) pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
161 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
163 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
167 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_ENABLE);
169 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr);
173 static int pm3393_interrupt_disable(struct cmac *cmac)
178 (void) pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
179 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
180 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
181 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
182 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
183 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
184 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
185 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
186 (void) pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
187 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
188 (void) pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
189 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
190 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
191 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
192 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
193 (void) pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
194 (void) pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
197 (void) pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
200 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
202 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
212 static int pm3393_interrupt_clear(struct cmac *cmac)
221 (void) pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
222 (void) pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
223 (void) pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
224 (void) pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
225 (void) pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
226 (void) pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
227 (void) pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
228 (void) pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
229 (void) pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
230 (void) pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
231 (void) pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
232 (void) pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
234 (void) pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
235 (void) pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
239 (void) pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
243 (void) t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
245 (void) t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
249 pl_intr = t1_read_reg_4(cmac->adapter, A_PL_CAUSE);
251 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr);
257 static int pm3393_interrupt_handler(struct cmac *cmac)
266 (void) pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
268 CH_DBG(cmac->adapter, INTR, "PM3393 intr cause 0x%x\n",
352 (void) pm3393_interrupt_clear(cmac);
357 static int pm3393_enable(struct cmac *cmac, int which)
360 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
366 if (cmac->instance->fc & PAUSE_RX)
368 if (cmac->instance->fc & PAUSE_TX)
370 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
373 cmac->instance->enabled |= which;
378 static int pm3393_enable_port(struct cmac *cmac, int which)
381 (void) pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
384 (void) memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
386 (void) pm3393_enable(cmac, which);
395 link_changed(cmac->adapter, 0);
400 static int pm3393_disable(struct cmac *cmac, int which)
403 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
405 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
413 cmac->instance->enabled &= ~which;
418 static int pm3393_loopback_enable(struct cmac *cmac)
424 static int pm3393_loopback_disable(struct cmac *cmac)
429 static int pm3393_set_mtu(struct cmac *cmac, int mtu)
431 int enabled = cmac->instance->enabled;
440 (void) pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
442 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
443 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
446 (void) pm3393_enable(cmac, enabled);
477 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
479 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
484 (void) pm3393_disable(cmac, MAC_DIRECTION_RX);
486 (void) pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
488 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
496 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
497 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
498 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
499 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
511 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
512 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
513 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
514 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
518 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
521 (void) pm3393_enable(cmac, MAC_DIRECTION_RX);
526 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
534 *fc = cmac->instance->fc;
538 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
548 if (fc != cmac->instance->fc) {
549 cmac->instance->fc = (u8) fc;
550 if (cmac->instance->enabled & MAC_DIRECTION_TX)
551 (void) pm3393_enable(cmac, MAC_DIRECTION_TX);
569 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
614 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
616 memcpy(mac_addr, cmac->instance->mac_addr, 6);
620 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
622 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
643 memcpy(cmac->instance->mac_addr, ma, 6);
651 (void) pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
654 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
655 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
656 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
659 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
660 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
661 (void) pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
667 (void) pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
669 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
671 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
672 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
673 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
676 (void) pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
679 (void) pm3393_enable(cmac, enabled);
683 static void pm3393_destroy(struct cmac *cmac)
685 t1_os_free((void *)cmac, sizeof(*cmac) + sizeof(cmac_instance));
731 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
733 struct cmac *cmac;
735 cmac = t1_os_malloc_wait_zero(sizeof(*cmac) + sizeof(cmac_instance));
736 if (!cmac)
739 cmac->ops = &pm3393_ops;
740 cmac->instance = (cmac_instance *) (cmac + 1);
741 cmac->adapter = adapter;
742 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
825 return cmac;