Lines Matching defs:bge_reg_set32
587 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
588 #pragma inline(bge_reg_set32)
591 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
595 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
798 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
1297 bge_reg_set32(bgep, NVM_CONFIG1_REG,
1373 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1720 bge_reg_set32(bgep, NVM_ACCESS_REG,
1739 bge_reg_set32(bgep, NVM_ACCESS_REG,
2569 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2690 bge_reg_set32(bgep, regno,
2717 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
3068 opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3484 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3586 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3625 bge_reg_set32(bgep, MSI_MODE_REG,
3743 bge_reg_set32(bgep, MODE_CONTROL_REG,
3754 bge_reg_set32(bgep, MODE_CONTROL_REG,
3942 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
4033 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4037 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4185 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4194 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4199 bge_reg_set32(bgep, MODE_CONTROL_REG,
4206 bge_reg_set32(bgep, MODE_CONTROL_REG,
4333 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4442 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4902 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);