Lines Matching defs:bge_reg_put32
574 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
575 #pragma inline(bge_reg_put32)
578 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
580 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
600 bge_reg_put32(bgep, regno, regval);
616 bge_reg_put32(bgep, regno, regval);
1133 bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1332 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1333 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1359 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1438 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1439 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1440 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1539 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1615 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1677 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1954 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1955 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
2680 bge_reg_put32(bgep,
2751 bge_reg_put32(bgep, regno, regval);
2795 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2797 bge_reg_put32(bgep, regno, 0);
2804 bge_reg_put32(bgep, regno, regval);
2845 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2847 bge_reg_put32(bgep, regno, 0);
2854 bge_reg_put32(bgep, regno, regval);
2907 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2919 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2931 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2941 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
2944 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3026 bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3029 bge_reg_put32(bgep, MAC_HASH_REG(i),
3063 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3215 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3216 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3410 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3513 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3518 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3584 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3591 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3608 bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3683 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3685 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3687 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3689 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3765 bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
3785 bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3787 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3789 bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3791 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3798 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3800 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3802 bge_reg_put32(bgep, MBUF_HIWAT_REG,
3809 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3811 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3814 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3832 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
3834 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
3850 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3852 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3854 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3909 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3914 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3919 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3925 bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3932 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3939 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3950 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3952 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3955 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3969 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3971 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3973 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3975 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3995 bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3997 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3999 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4137 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4158 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4163 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4344 bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4549 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4550 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4551 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4552 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4553 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4554 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4603 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
5761 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5762 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5811 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5895 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);