Lines Matching refs:dev
95 static void audigyls_configure_mixer(audigyls_dev_t *dev);
149 read_chan(audigyls_dev_t *dev, int reg, int chn)
153 mutex_enter(&dev->low_mutex);
155 OUTL(dev, PR, (reg << 16) | (chn & 0xffff));
157 val = INL(dev, DR);
158 mutex_exit(&dev->low_mutex);
164 write_chan(audigyls_dev_t *dev, int reg, int chn, uint32_t value)
166 mutex_enter(&dev->low_mutex);
168 OUTL(dev, PR, (reg << 16) | (chn & 0x7));
170 OUTL(dev, DR, value);
171 mutex_exit(&dev->low_mutex);
175 read_reg(audigyls_dev_t *dev, int reg)
177 return (read_chan(dev, reg, 0));
181 write_reg(audigyls_dev_t *dev, int reg, uint32_t value)
183 write_chan(dev, reg, 0, value);
190 audigyls_dev_t *dev = arg;
194 mutex_enter(&dev->low_mutex);
195 OUTB(dev, AC97A, index);
197 if (INB(dev, AC97A) & 0x80)
201 mutex_exit(&dev->low_mutex);
204 dtemp = INW(dev, AC97D);
205 mutex_exit(&dev->low_mutex);
213 audigyls_dev_t *dev = arg;
216 mutex_enter(&dev->low_mutex);
217 OUTB(dev, AC97A, index);
219 if (INB(dev, AC97A) & 0x80)
223 mutex_exit(&dev->low_mutex);
226 OUTW(dev, AC97D, data);
227 mutex_exit(&dev->low_mutex);
231 select_digital_enable(audigyls_dev_t *dev, int mode)
239 write_reg(dev, SPC, 0x00000f00);
241 write_reg(dev, SPC, 0x0000000f);
247 audigyls_i2c_write(audigyls_dev_t *dev, int reg, int data)
253 write_reg(dev, I2C_1, tmp);
255 tmp = read_reg(dev, I2C_A) & ~0x6fe;
258 write_reg(dev, I2C_A, tmp);
262 tmp = read_reg(dev, I2C_A);
279 audigyls_spi_write(audigyls_dev_t *dev, int data)
285 tmp = read_reg(dev, SPI);
287 write_reg(dev, SPI, orig | data);
292 tmp = read_reg(dev, SPI);
312 audigyls_dev_t *dev = port->dev;
316 mutex_enter(&dev->mutex);
321 mutex_exit(&dev->mutex);
336 audigyls_dev_t *dev = port->dev;
339 mutex_enter(&dev->mutex);
345 write_chan(dev, PTCA, 0, 0);
346 write_chan(dev, CPFA, 0, 0);
347 write_chan(dev, CPCAV, 0, 0);
348 write_chan(dev, PTCA, 1, 0);
349 write_chan(dev, CPFA, 1, 0);
350 write_chan(dev, CPCAV, 1, 0);
351 write_chan(dev, PTCA, 3, 0);
352 write_chan(dev, CPFA, 3, 0);
353 write_chan(dev, CPCAV, 3, 0);
355 tmp = read_reg(dev, SA);
359 write_reg(dev, SA, tmp);
363 write_chan(dev, CRFA, 2, 0);
364 write_chan(dev, CRCAV, 2, 0);
366 tmp = read_reg(dev, SA);
368 write_reg(dev, SA, tmp);
372 mutex_exit(&dev->mutex);
380 audigyls_dev_t *dev = port->dev;
383 mutex_enter(&dev->mutex);
387 tmp = read_reg(dev, SA);
391 write_reg(dev, SA, tmp);
395 tmp = read_reg(dev, SA);
397 write_reg(dev, SA, tmp);
401 mutex_exit(&dev->mutex);
441 audigyls_dev_t *dev = port->dev;
445 mutex_enter(&dev->mutex);
448 offset = read_chan(dev, CPFA, 0);
450 offset = read_chan(dev, CRFA, 2);
465 mutex_exit(&dev->mutex);
486 audigyls_alloc_port(audigyls_dev_t *dev, int num)
496 adev = dev->adev;
498 dev->port[num] = port;
499 port->dev = dev;
523 if (ddi_dma_alloc_handle(dev->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
557 audigyls_del_controls(audigyls_dev_t *dev)
560 if (dev->controls[i].ctrl) {
561 audio_dev_del_control(dev->controls[i].ctrl);
562 dev->controls[i].ctrl = NULL;
568 audigyls_destroy(audigyls_dev_t *dev)
570 mutex_destroy(&dev->mutex);
571 mutex_destroy(&dev->low_mutex);
574 audigyls_port_t *port = dev->port[i];
578 audio_dev_remove_engine(dev->adev, port->engine);
593 if (dev->ac97 != NULL) {
594 ac97_free(dev->ac97);
597 audigyls_del_controls(dev);
599 if (dev->adev != NULL) {
600 audio_dev_free(dev->adev);
602 if (dev->regsh != NULL) {
603 ddi_regs_map_free(&dev->regsh);
605 if (dev->pcih != NULL) {
606 pci_config_teardown(&dev->pcih);
608 kmem_free(dev, sizeof (*dev));
612 audigyls_hwinit(audigyls_dev_t *dev)
628 select_digital_enable(dev, dev->digital_enable);
662 if (dev->ac97)
663 OUTL(dev, GPIO, 0x005f03a3);
666 OUTL(dev, GPIO, 0x005f4301);
668 audigyls_i2c_write(dev, 0x15, 0x2);
672 if (!audigyls_spi_write(dev, spi_dac[i]) &&
680 OUTL(dev, IER, 0);
681 OUTL(dev, HC, 0x00000009); /* Enable audio, use 48 kHz */
683 tmp = read_chan(dev, SRCTL, 0);
684 if (dev->ac97)
689 write_chan(dev, SRCTL, 0, tmp);
691 write_reg(dev, HMIXMAP_I2S, 0x76543210); /* Default out route */
692 write_reg(dev, AUDCTL, 0x0f0f003f); /* Enable all outputs */
695 write_reg(dev, SA, 0);
702 write_chan(dev, PTBA, i, 0);
703 write_chan(dev, PTBS, i, 0);
704 write_chan(dev, PTCA, i, 0);
706 write_chan(dev, CPFA, i, 0);
707 write_chan(dev, PFEA, i, 0);
708 write_chan(dev, CPCAV, i, 0);
710 write_chan(dev, CRFA, i, 0);
711 write_chan(dev, CRCAV, i, 0);
718 port = dev->port[AUDIGYLS_PLAY_PORT];
721 write_chan(dev, PFBA, 0, paddr);
722 write_chan(dev, PFBS, 0, chunksz << 16);
724 write_chan(dev, PFBA, 1, paddr);
725 write_chan(dev, PFBS, 1, chunksz << 16);
727 write_chan(dev, PFBA, 3, paddr);
728 write_chan(dev, PFBS, 3, chunksz << 16);
731 port = dev->port[AUDIGYLS_REC_PORT];
734 write_chan(dev, RFBA, 2, paddr);
735 write_chan(dev, RFBS, 2, chunksz << 16);
738 tmp = read_chan(dev, SRCTL, 0) & ~0x0303c00f;
739 write_chan(dev, SRCTL, 0, tmp);
741 write_reg(dev, SCS0, 0x02108004); /* Audio */
742 write_reg(dev, SCS1, 0x02108004); /* Audio */
743 write_reg(dev, SCS2, 0x02108004); /* Audio */
744 write_reg(dev, SCS3, 0x02108004); /* Audio */
774 audigyls_configure_mixer(audigyls_dev_t *dev)
780 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_FRONT].val, 8);
782 write_chan(dev, MIXVOL_I2S, 0, r);
785 r = 0xffff - audigyls_stereo_scale(dev->controls[CTL_SURROUND].val, 8);
787 write_chan(dev, MIXVOL_I2S, 3, r);
790 v1 = 255 - SCALE(dev->controls[CTL_CENTER].val, 8);
791 v2 = 255 - SCALE(dev->controls[CTL_LFE].val, 8);
794 write_chan(dev, MIXVOL_I2S, 1, r);
797 r = dev->controls[CTL_SPREAD].val ? 0x10101010 : 0x76543210;
798 write_reg(dev, HMIXMAP_I2S, r);
803 v1 = dev->controls[CTL_RECORDVOL].val;
804 if (dev->ac97_recgain && !dev->controls[CTL_LOOP].val) {
809 (void) ac97_control_set(dev->ac97_recgain, v1);
810 write_reg(dev, P17RECVOLL, 0x30303030);
811 write_reg(dev, P17RECVOLH, 0x30303030);
818 write_reg(dev, P17RECVOLL, r);
819 write_reg(dev, P17RECVOLH, r);
823 if (dev->ac97) {
825 write_chan(dev, SRCTL, 1, 0x30303030);
826 write_reg(dev, SMIXMAP_I2S, 0x10101076);
829 r = 255 - SCALE(dev->controls[CTL_MONGAIN].val, 8);
830 write_chan(dev, SRCTL, 1, 0xffff0000 | r << 8 | r);
832 write_reg(dev, SMIXMAP_I2S, 0x10101076);
834 write_reg(dev, SMIXMAP_I2S, 0x10101010);
839 if (dev->ac97_recsrc != NULL) {
840 (void) ac97_control_set(dev->ac97_recsrc,
841 dev->controls[CTL_RECSRC].val);
844 switch (dev->controls[CTL_RECSRC].val) {
846 audigyls_i2c_write(dev, 0x15, 0x2); /* Mic */
847 OUTL(dev, GPIO, INL(dev, GPIO) | 0x400);
851 audigyls_i2c_write(dev, 0x15, 0x4); /* Line */
852 OUTL(dev, GPIO, INL(dev, GPIO) & ~0x400);
860 if (dev->controls[CTL_LOOP].val) {
873 if (dev->ac97_recsrc != NULL) {
883 write_reg(dev, P17RECSEL, r);
890 audigyls_dev_t *dev = pc->dev;
913 if (((1U << val) & (dev->recmask)) == 0) {
929 mutex_enter(&dev->mutex);
931 audigyls_configure_mixer(dev);
933 mutex_exit(&dev->mutex);
942 audigyls_dev_t *dev = pc->dev;
944 mutex_enter(&dev->mutex);
946 mutex_exit(&dev->mutex);
951 audigyls_alloc_ctrl(audigyls_dev_t *dev, uint32_t num, uint64_t val)
958 pc = &dev->controls[num];
960 pc->dev = dev;
1014 if (dev->ac97_recsrc) {
1019 adp = ac97_control_desc(dev->ac97_recsrc);
1036 dev->recmask |= (1 << i);
1039 desc.acd_minvalue = desc.acd_maxvalue = dev->recmask;
1041 dev->recmask = 3;
1050 ASSERT(!dev->ac97);
1076 pc->ctrl = audio_dev_add_control(dev->adev, &desc,
1081 audigyls_add_controls(audigyls_dev_t *dev)
1083 audio_dev_add_soft_volume(dev->adev);
1085 audigyls_alloc_ctrl(dev, CTL_FRONT, 75 | (75 << 8));
1086 audigyls_alloc_ctrl(dev, CTL_SURROUND, 75 | (75 << 8));
1087 audigyls_alloc_ctrl(dev, CTL_CENTER, 75);
1088 audigyls_alloc_ctrl(dev, CTL_LFE, 75);
1089 audigyls_alloc_ctrl(dev, CTL_RECORDVOL, 75 | (75 << 8));
1090 audigyls_alloc_ctrl(dev, CTL_RECSRC, 1);
1091 audigyls_alloc_ctrl(dev, CTL_SPREAD, 0);
1092 audigyls_alloc_ctrl(dev, CTL_LOOP, 0);
1093 if (!dev->ac97) {
1094 audigyls_alloc_ctrl(dev, CTL_MONGAIN, 0);
1103 audigyls_dev_t *dev;
1108 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP);
1109 dev->dip = dip;
1110 ddi_set_driver_private(dip, dev);
1111 mutex_init(&dev->mutex, NULL, MUTEX_DRIVER, NULL);
1112 mutex_init(&dev->low_mutex, NULL, MUTEX_DRIVER, NULL);
1114 if ((dev->adev = audio_dev_alloc(dip, 0)) == NULL) {
1120 audio_dev_warn(dev->adev, "pci_config_setup failed");
1123 dev->pcih = pcih;
1132 audio_dev_warn(dev->adev, "Hardware not recognized "
1133 "(vendor=%x, dev=%x)", vendor, device);
1141 if ((ddi_regs_map_setup(dip, 1, &dev->base, 0, 0, &dev_attr,
1142 &dev->regsh)) != DDI_SUCCESS) {
1143 audio_dev_warn(dev->adev, "failed to map registers");
1148 dev->digital_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dev->dip,
1197 audio_dev_set_description(dev->adev, name);
1199 audio_dev_set_version(dev->adev, version);
1205 dev->ac97 = ac97_allocate(dev->adev, dip,
1206 audigyls_read_ac97, audigyls_write_ac97, dev);
1207 if (dev->ac97 == NULL) {
1208 audio_dev_warn(dev->adev,
1213 ac97_probe_controls(dev->ac97);
1217 ctrl = ac97_control_find(dev->ac97,
1224 dev->ac97_recgain = ac97_control_find(dev->ac97,
1226 dev->ac97_recsrc = ac97_control_find(dev->ac97,
1230 audigyls_add_controls(dev);
1232 if (dev->ac97) {
1233 ac97_register_controls(dev->ac97);
1236 if (audigyls_alloc_port(dev, AUDIGYLS_PLAY_PORT) != DDI_SUCCESS)
1238 if (audigyls_alloc_port(dev, AUDIGYLS_REC_PORT) != DDI_SUCCESS)
1241 audigyls_hwinit(dev);
1243 audigyls_configure_mixer(dev);
1245 if (audio_dev_register(dev->adev) != DDI_SUCCESS) {
1246 audio_dev_warn(dev->adev, "unable to register with framework");
1255 audigyls_destroy(dev);
1262 audigyls_dev_t *dev;
1264 dev = ddi_get_driver_private(dip);
1266 audigyls_hwinit(dev);
1269 if (dev->ac97)
1270 ac97_reset(dev->ac97);
1272 audio_dev_resume(dev->adev);
1278 audigyls_detach(audigyls_dev_t *dev)
1280 if (audio_dev_unregister(dev->adev) != DDI_SUCCESS)
1283 audigyls_destroy(dev);
1288 audigyls_suspend(audigyls_dev_t *dev)
1290 audio_dev_suspend(dev->adev);
1372 audigyls_dev_t *dev;
1374 dev = ddi_get_driver_private(dip);
1378 return (audigyls_detach(dev));
1381 return (audigyls_suspend(dev));
1391 audigyls_dev_t *dev;
1397 dev = ddi_get_driver_private(dip);
1399 write_reg(dev, SA, 0);
1400 OUTL(dev, IER, 0); /* Interrupt disable */
1401 write_reg(dev, AIE, 0); /* Disable audio interrupts */
1402 status = INL(dev, IPR);
1403 OUTL(dev, IPR, status); /* Acknowledge */