239 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value)
272 		emu10k_write_reg(devc, SRDA, voice, srda);
278 		emu10k_write_reg(devc, FXRT, voice, fxrt);
285 	emu10k_write_reg(devc, reg, 0, value);
322 	emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]);
336 	emu10k_write_reg(devc, VEDS, voice, 0x0);	/* OFF */
337 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
338 	emu10k_write_reg(devc, CVCF, voice, 0xffff);
348 	emu10k_write_reg(devc, CPF, voice, 0x8000);
355 	emu10k_write_reg(devc, SDL, voice, loop_end);
356 	emu10k_write_reg(devc, SCSA, voice, loop_start);
357 	emu10k_write_reg(devc, PTAB, voice, 0);
361 	emu10k_write_reg(devc, QKBCA, voice, start_pos);
363 	emu10k_write_reg(devc, Z1, voice, 0);
364 	emu10k_write_reg(devc, Z2, voice, 0);
367 	emu10k_write_reg(devc, MAPA, voice,
369 	emu10k_write_reg(devc, MAPB, voice,
372 	emu10k_write_reg(devc, VTFT, voice, 0x0000ffff);
373 	emu10k_write_reg(devc, CVCF, voice, 0x0000ffff);
374 	emu10k_write_reg(devc, MEHA, voice, 0);
375 	emu10k_write_reg(devc, MEDS, voice, 0x7f);
376 	emu10k_write_reg(devc, MLV, voice, 0x8000);
377 	emu10k_write_reg(devc, VLV, voice, 0x8000);
378 	emu10k_write_reg(devc, VFM, voice, 0);
379 	emu10k_write_reg(devc, TMFQ, voice, 0);
380 	emu10k_write_reg(devc, VVFQ, voice, 0);
381 	emu10k_write_reg(devc, MEV, voice, 0x8000);
382 	emu10k_write_reg(devc, VEHA, voice, 0x7f7f);	/* OK */
384 	emu10k_write_reg(devc, VEV, voice, 0x8000);
385 	emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f);
386 	emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00);
512 	emu10k_write_reg(devc, SOLL + offs, 0, tmp);
608 		emu10k_write_reg(devc, CD0 + i, voice, sample);
610 	emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0);
611 	emu10k_write_reg(devc, CCR_READADDRESS, voice, cra);
612 	emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis);
615 	emu10k_write_reg(devc, IFA, voice, 0xff00);
616 	emu10k_write_reg(devc, VTFT, voice, 0xffffffff);
617 	emu10k_write_reg(devc, CVCF, voice, 0xffffffff);
622 	emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target);
623 	emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target);
624 	emu10k_write_reg(devc, IP, voice, initial_pitch);
630 	emu10k_write_reg(devc, IFA, voice, 0xffff);
631 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
632 	emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0);
633 	emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0);
634 	emu10k_write_reg(devc, IP, voice, 0);
646 	emu10k_write_reg(devc, IFA, voice, 0xffff);
648 	emu10k_write_reg(devc, VEDS, voice, 0x0);
650 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
652 	emu10k_write_reg(devc, PTAB, voice, 0x0);
655 	emu10k_write_reg(devc, IFA, voice + 1, 0xffff);
656 	emu10k_write_reg(devc, VEDS, voice + 1, 0x0);
657 	emu10k_write_reg(devc, VTFT, voice + 1, 0xffff);
658 	emu10k_write_reg(devc, PTAB, voice + 1, 0x0);
687 	emu10k_write_reg(devc, VEDS, 0, 0x7f7f);
688 	emu10k_write_reg(devc, VEDS, 1, 0x7f7f);
689 	emu10k_write_reg(devc, VEDS, 2, 0x7f7f);
690 	emu10k_write_reg(devc, VEDS, 3, 0x7f7f);
691 	emu10k_write_reg(devc, VEDS, 4, 0x7f7f);
692 	emu10k_write_reg(devc, VEDS, 5, 0x7f7f);
693 	emu10k_write_reg(devc, VEDS, 6, 0x7f7f);
694 	emu10k_write_reg(devc, VEDS, 7, 0x7f7f);
793 	emu10k_write_reg(devc, ADCSR, 0, tmp);	/* GO */
804 	emu10k_write_reg(devc, ADCSR, 0, 0);
831 	emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr);
832 	emu10k_write_reg(devc, ADCBS, 0, sz);
833 	emu10k_write_reg(devc, ADCSR, 0, 0);	/* reset for phase */
1049 	emu10k_write_reg(devc, VEDS, voice, 0x0);
1050 	emu10k_write_reg(devc, IP, voice, 0x0);
1051 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
1052 	emu10k_write_reg(devc, CVCF, voice, 0xffff);
1053 	emu10k_write_reg(devc, PTAB, voice, 0x0);
1054 	emu10k_write_reg(devc, CPF, voice, 0x0);
1055 	emu10k_write_reg(devc, CCR, voice, 0x0);
1056 	emu10k_write_reg(devc, SCSA, voice, 0x0);
1057 	emu10k_write_reg(devc, SDL, voice, 0x10);
1058 	emu10k_write_reg(devc, QKBCA, voice, 0x0);
1059 	emu10k_write_reg(devc, Z1, voice, 0x0);
1060 	emu10k_write_reg(devc, Z2, voice, 0x0);
1063 		emu10k_write_reg(devc, SRDA, voice, 0x03020100);
1065 		emu10k_write_reg(devc, FXRT, voice, 0x32100000);
1067 	emu10k_write_reg(devc, MEHA, voice, 0x0);
1068 	emu10k_write_reg(devc, MEDS, voice, 0x0);
1069 	emu10k_write_reg(devc, IFA, voice, 0xffff);
1070 	emu10k_write_reg(devc, PEFE, voice, 0x0);
1071 	emu10k_write_reg(devc, VFM, voice, 0x0);
1072 	emu10k_write_reg(devc, TMFQ, voice, 24);
1073 	emu10k_write_reg(devc, VVFQ, voice, 24);
1074 	emu10k_write_reg(devc, TMPE, voice, 0x0);
1075 	emu10k_write_reg(devc, VLV, voice, 0x0);
1076 	emu10k_write_reg(devc, MLV, voice, 0x0);
1077 	emu10k_write_reg(devc, VEHA, voice, 0x0);
1078 	emu10k_write_reg(devc, VEV, voice, 0x0);
1079 	emu10k_write_reg(devc, MEV, voice, 0x0);
1082 		emu10k_write_reg(devc, CSBA, voice, 0x0);
1083 		emu10k_write_reg(devc, CSDC, voice, 0x0);
1084 		emu10k_write_reg(devc, CSFE, voice, 0x0);
1085 		emu10k_write_reg(devc, CSHG, voice, 0x0);
1086 		emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f);
1099 	emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE);
1106 	emu10k_write_reg(devc, MBS, 0, 0x0);
1107 	emu10k_write_reg(devc, MBA, 0, 0x0);
1108 	emu10k_write_reg(devc, FXBS, 0, 0x0);
1109 	emu10k_write_reg(devc, FXBA, 0, 0x0);
1110 	emu10k_write_reg(devc, ADCBS, 0, 0x0);
1111 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
1115 	emu10k_write_reg(devc, CLIEL, 0, 0x0);
1116 	emu10k_write_reg(devc, CLIEH, 0, 0x0);
1118 		emu10k_write_reg(devc, HLIEL, 0, 0x0);
1119 		emu10k_write_reg(devc, HLIEH, 0, 0x0);
1121 	emu10k_write_reg(devc, CLIPL, 0, 0xffffffff);
1122 	emu10k_write_reg(devc, CLIPH, 0, 0xffffffff);
1123 	emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1124 	emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1128 		emu10k_write_reg(devc, SOC, 0, 0xf00);	/* ?? */
1129 		emu10k_write_reg(devc, AC97SLOT, 0, 0x3);	/* ?? */
1135 	emu10k_write_reg(devc, SCS0, 0, 0x2109204);
1136 	emu10k_write_reg(devc, SCS1, 0, 0x2109204);
1137 	emu10k_write_reg(devc, SCS2, 0, 0x2109204);
1139 	emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr);
1142 	emu10k_write_reg(devc, TCBA, 0, 0x0);
1143 	emu10k_write_reg(devc, TCBS, 0, 0x4);
1154 	emu10k_write_reg(devc, AC97SLOT, 0, reg);
1164 		emu10k_write_reg(devc, EHC, 0, tmp);
1165 		/* emu10k_write_reg (devc, SOC, 0, 0x00000000); */
1200 		emu10k_write_reg(devc, EHC, 0, tmp);
1218 	emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1219 	emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1327 	emu10k_write_reg(devc, gpr + GPR0, 0, value);
1818 		emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]);
1853 		emu10k_write_reg(devc, AUDIGY_DBG, 0, 0);
1868 		emu10k_write_reg(devc, DBG, 0, 0);
2281 		emu10k_write_reg(devc, VEDS, i, 0);
2284 		emu10k_write_reg(devc, VTFT, i, 0);
2285 		emu10k_write_reg(devc, CVCF, i, 0);
2286 		emu10k_write_reg(devc, PTAB, i, 0);
2287 		emu10k_write_reg(devc, CPF, i, 0);
2298 	emu10k_write_reg(devc, ADCSR, 0, 0x0);
2299 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
2300 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
2302 	emu10k_write_reg(devc, PTBA, 0, 0);

Indexes created Fri Sep 13 23:15:19 MDT 2024