Lines Matching defs:devc
179 emu10k_devc_t *devc = arg;
182 mutex_enter(&devc->mutex);
183 OUTB(devc, index, devc->regs + 0x1e);
185 if (INB(devc, devc->regs + 0x1e) & 0x80)
189 mutex_exit(&devc->mutex);
192 dtemp = INW(devc, devc->regs + 0x1c);
194 mutex_exit(&devc->mutex);
202 emu10k_devc_t *devc = arg;
205 mutex_enter(&devc->mutex);
207 OUTB(devc, index, devc->regs + 0x1e);
209 if (INB(devc, devc->regs + 0x1e) & 0x80)
211 OUTW(devc, data, devc->regs + 0x1c);
213 mutex_exit(&devc->mutex);
217 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn)
221 ptr_addr_mask = (devc->feature_mask &
225 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */
226 val = INL(devc, devc->regs + 0x04); /* Data */
239 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value)
243 ptr_addr_mask = (devc->feature_mask &
247 OUTL(devc, ptr, devc->regs + 0x00); /* Pointer */
254 value |= INL(devc, devc->regs + 0x04) & ~mask; /* data */
256 OUTL(devc, value, devc->regs + 0x04); /* Data */
260 emu10k_write_routing(emu10k_devc_t *devc, int voice, unsigned char *routing)
266 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
272 emu10k_write_reg(devc, SRDA, voice, srda);
278 emu10k_write_reg(devc, FXRT, voice, fxrt);
283 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value)
285 emu10k_write_reg(devc, reg, 0, value);
295 emu10k_devc_t *devc = portc->devc;
321 tmp = emu10k_read_reg(devc, PTAB, voice) & 0xffff0000;
322 emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]);
328 emu10k_devc_t *devc = portc->devc;
336 emu10k_write_reg(devc, VEDS, voice, 0x0); /* OFF */
337 emu10k_write_reg(devc, VTFT, voice, 0xffff);
338 emu10k_write_reg(devc, CVCF, voice, 0xffff);
348 emu10k_write_reg(devc, CPF, voice, 0x8000);
355 emu10k_write_reg(devc, SDL, voice, loop_end);
356 emu10k_write_reg(devc, SCSA, voice, loop_start);
357 emu10k_write_reg(devc, PTAB, voice, 0);
361 emu10k_write_reg(devc, QKBCA, voice, start_pos);
363 emu10k_write_reg(devc, Z1, voice, 0);
364 emu10k_write_reg(devc, Z2, voice, 0);
367 emu10k_write_reg(devc, MAPA, voice,
368 0x1fff | (devc->silence_paddr << 1));
369 emu10k_write_reg(devc, MAPB, voice,
370 0x1fff | (devc->silence_paddr << 1));
372 emu10k_write_reg(devc, VTFT, voice, 0x0000ffff);
373 emu10k_write_reg(devc, CVCF, voice, 0x0000ffff);
374 emu10k_write_reg(devc, MEHA, voice, 0);
375 emu10k_write_reg(devc, MEDS, voice, 0x7f);
376 emu10k_write_reg(devc, MLV, voice, 0x8000);
377 emu10k_write_reg(devc, VLV, voice, 0x8000);
378 emu10k_write_reg(devc, VFM, voice, 0);
379 emu10k_write_reg(devc, TMFQ, voice, 0);
380 emu10k_write_reg(devc, VVFQ, voice, 0);
381 emu10k_write_reg(devc, MEV, voice, 0x8000);
382 emu10k_write_reg(devc, VEHA, voice, 0x7f7f); /* OK */
384 emu10k_write_reg(devc, VEV, voice, 0x8000);
385 emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f);
386 emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00);
393 emu10k_devc_t *devc = portc->devc;
401 mutex_enter(&devc->mutex);
403 mutex_exit(&devc->mutex);
418 emu10k_devc_t *devc = portc->devc;
420 mutex_enter(&devc->mutex);
423 mutex_exit(&devc->mutex);
431 emu10k_devc_t *devc = portc->devc;
433 mutex_enter(&devc->mutex);
435 mutex_exit(&devc->mutex);
475 emu10k_devc_t *devc = portc->devc;
478 mutex_enter(&devc->mutex);
481 mutex_exit(&devc->mutex);
498 emu10k_set_loop_stop(emu10k_devc_t *devc, int voice, int s)
507 tmp = emu10k_read_reg(devc, SOLL + offs, 0);
512 emu10k_write_reg(devc, SOLL + offs, 0, tmp);
596 emu10k_prepare_voice(emu10k_devc_t *devc, int voice)
608 emu10k_write_reg(devc, CD0 + i, voice, sample);
610 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0);
611 emu10k_write_reg(devc, CCR_READADDRESS, voice, cra);
612 emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis);
615 emu10k_write_reg(devc, IFA, voice, 0xff00);
616 emu10k_write_reg(devc, VTFT, voice, 0xffffffff);
617 emu10k_write_reg(devc, CVCF, voice, 0xffffffff);
618 emu10k_set_loop_stop(devc, voice, 0);
622 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target);
623 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target);
624 emu10k_write_reg(devc, IP, voice, initial_pitch);
628 emu10k_stop_voice(emu10k_devc_t *devc, int voice)
630 emu10k_write_reg(devc, IFA, voice, 0xffff);
631 emu10k_write_reg(devc, VTFT, voice, 0xffff);
632 emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0);
633 emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0);
634 emu10k_write_reg(devc, IP, voice, 0);
635 emu10k_set_loop_stop(devc, voice, 1);
642 emu10k_devc_t *devc = portc->devc;
646 emu10k_write_reg(devc, IFA, voice, 0xffff);
648 emu10k_write_reg(devc, VEDS, voice, 0x0);
650 emu10k_write_reg(devc, VTFT, voice, 0xffff);
652 emu10k_write_reg(devc, PTAB, voice, 0x0);
655 emu10k_write_reg(devc, IFA, voice + 1, 0xffff);
656 emu10k_write_reg(devc, VEDS, voice + 1, 0x0);
657 emu10k_write_reg(devc, VTFT, voice + 1, 0xffff);
658 emu10k_write_reg(devc, PTAB, voice + 1, 0x0);
664 emu10k_write_routing(devc, voice, routing);
665 emu10k_write_routing(devc, voice + 1, routing);
671 emu10k_devc_t *devc = portc->devc;
673 ASSERT(mutex_owned(&devc->mutex));
674 emu10k_prepare_voice(devc, 0);
675 emu10k_prepare_voice(devc, 1);
677 emu10k_prepare_voice(devc, 2);
678 emu10k_prepare_voice(devc, 3);
680 emu10k_prepare_voice(devc, 4);
681 emu10k_prepare_voice(devc, 5);
683 emu10k_prepare_voice(devc, 6);
684 emu10k_prepare_voice(devc, 7);
687 emu10k_write_reg(devc, VEDS, 0, 0x7f7f);
688 emu10k_write_reg(devc, VEDS, 1, 0x7f7f);
689 emu10k_write_reg(devc, VEDS, 2, 0x7f7f);
690 emu10k_write_reg(devc, VEDS, 3, 0x7f7f);
691 emu10k_write_reg(devc, VEDS, 4, 0x7f7f);
692 emu10k_write_reg(devc, VEDS, 5, 0x7f7f);
693 emu10k_write_reg(devc, VEDS, 6, 0x7f7f);
694 emu10k_write_reg(devc, VEDS, 7, 0x7f7f);
702 emu10k_devc_t *devc = portc->devc;
704 emu10k_stop_voice(devc, 0);
705 emu10k_stop_voice(devc, 1);
706 emu10k_stop_voice(devc, 2);
707 emu10k_stop_voice(devc, 3);
708 emu10k_stop_voice(devc, 4);
709 emu10k_stop_voice(devc, 5);
710 emu10k_stop_voice(devc, 6);
711 emu10k_stop_voice(devc, 7);
719 emu10k_devc_t *devc = portc->devc;
724 if (devc->feature_mask & SB_71) {
729 } else if (devc->feature_mask & SB_51) {
746 emu10k_devc_t *devc = portc->devc;
752 pos = emu10k_read_reg(devc, QKBCA, 0) & 0xffffff;
785 emu10k_devc_t *devc = portc->devc;
789 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
793 emu10k_write_reg(devc, ADCSR, 0, tmp); /* GO */
801 emu10k_devc_t *devc = portc->devc;
803 ASSERT(mutex_owned(&devc->mutex));
804 emu10k_write_reg(devc, ADCSR, 0, 0);
811 emu10k_devc_t *devc = portc->devc;
831 emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr);
832 emu10k_write_reg(devc, ADCBS, 0, sz);
833 emu10k_write_reg(devc, ADCSR, 0, 0); /* reset for phase */
840 emu10k_devc_t *devc = portc->devc;
844 pos = emu10k_read_reg(devc,
845 (devc->feature_mask & SB_LIVE) ? MIDX : ADCIDX, 0);
857 emu10k_alloc_port(emu10k_devc_t *devc, int num)
868 adev = devc->adev;
870 devc->portc[num] = portc;
871 portc->devc = devc;
873 portc->memptr = devc->audio_memptr;
874 devc->audio_memptr += (DMABUF_SIZE + 4095) & ~4095;
922 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
943 if ((devc->feature_mask & SB_LIVE) &&
959 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
975 emu10k_destroy(emu10k_devc_t *devc)
977 mutex_destroy(&devc->mutex);
979 if (devc->silence_paddr) {
980 (void) ddi_dma_unbind_handle(devc->silence_dmah);
982 if (devc->silence_acch) {
983 ddi_dma_mem_free(&devc->silence_acch);
985 if (devc->silence_dmah) {
986 ddi_dma_free_handle(&devc->silence_dmah);
989 if (devc->pt_paddr) {
990 (void) ddi_dma_unbind_handle(devc->pt_dmah);
992 if (devc->pt_acch) {
993 ddi_dma_mem_free(&devc->pt_acch);
995 if (devc->pt_dmah) {
996 ddi_dma_free_handle(&devc->pt_dmah);
1001 emu10k_ctrl_t *ec = &devc->ctrls[i];
1009 emu10k_portc_t *portc = devc->portc[i];
1013 audio_dev_remove_engine(devc->adev, portc->engine);
1028 if (devc->ac97 != NULL) {
1029 ac97_free(devc->ac97);
1031 if (devc->adev != NULL) {
1032 audio_dev_free(devc->adev);
1034 if (devc->regsh != NULL) {
1035 ddi_regs_map_free(&devc->regsh);
1037 if (devc->pcih != NULL) {
1038 pci_config_teardown(&devc->pcih);
1041 kmem_free(devc, sizeof (*devc));
1045 emu10k_init_voice(emu10k_devc_t *devc, int voice)
1047 emu10k_set_loop_stop(devc, voice, 1);
1049 emu10k_write_reg(devc, VEDS, voice, 0x0);
1050 emu10k_write_reg(devc, IP, voice, 0x0);
1051 emu10k_write_reg(devc, VTFT, voice, 0xffff);
1052 emu10k_write_reg(devc, CVCF, voice, 0xffff);
1053 emu10k_write_reg(devc, PTAB, voice, 0x0);
1054 emu10k_write_reg(devc, CPF, voice, 0x0);
1055 emu10k_write_reg(devc, CCR, voice, 0x0);
1056 emu10k_write_reg(devc, SCSA, voice, 0x0);
1057 emu10k_write_reg(devc, SDL, voice, 0x10);
1058 emu10k_write_reg(devc, QKBCA, voice, 0x0);
1059 emu10k_write_reg(devc, Z1, voice, 0x0);
1060 emu10k_write_reg(devc, Z2, voice, 0x0);
1062 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
1063 emu10k_write_reg(devc, SRDA, voice, 0x03020100);
1065 emu10k_write_reg(devc, FXRT, voice, 0x32100000);
1067 emu10k_write_reg(devc, MEHA, voice, 0x0);
1068 emu10k_write_reg(devc, MEDS, voice, 0x0);
1069 emu10k_write_reg(devc, IFA, voice, 0xffff);
1070 emu10k_write_reg(devc, PEFE, voice, 0x0);
1071 emu10k_write_reg(devc, VFM, voice, 0x0);
1072 emu10k_write_reg(devc, TMFQ, voice, 24);
1073 emu10k_write_reg(devc, VVFQ, voice, 24);
1074 emu10k_write_reg(devc, TMPE, voice, 0x0);
1075 emu10k_write_reg(devc, VLV, voice, 0x0);
1076 emu10k_write_reg(devc, MLV, voice, 0x0);
1077 emu10k_write_reg(devc, VEHA, voice, 0x0);
1078 emu10k_write_reg(devc, VEV, voice, 0x0);
1079 emu10k_write_reg(devc, MEV, voice, 0x0);
1081 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1082 emu10k_write_reg(devc, CSBA, voice, 0x0);
1083 emu10k_write_reg(devc, CSDC, voice, 0x0);
1084 emu10k_write_reg(devc, CSFE, voice, 0x0);
1085 emu10k_write_reg(devc, CSHG, voice, 0x0);
1086 emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f);
1091 emu10k_hwinit(emu10k_devc_t *devc)
1097 ASSERT(mutex_owned(&devc->mutex));
1099 emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE);
1101 OUTL(devc, 0x00000000, devc->regs + 0x0c); /* Intr disable */
1102 OUTL(devc, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
1104 devc->regs + HCFG);
1106 emu10k_write_reg(devc, MBS, 0, 0x0);
1107 emu10k_write_reg(devc, MBA, 0, 0x0);
1108 emu10k_write_reg(devc, FXBS, 0, 0x0);
1109 emu10k_write_reg(devc, FXBA, 0, 0x0);
1110 emu10k_write_reg(devc, ADCBS, 0, 0x0);
1111 emu10k_write_reg(devc, ADCBA, 0, 0x0);
1114 OUTL(devc, 0, devc->regs + IE);
1115 emu10k_write_reg(devc, CLIEL, 0, 0x0);
1116 emu10k_write_reg(devc, CLIEH, 0, 0x0);
1117 if (!(devc->feature_mask & SB_LIVE)) {
1118 emu10k_write_reg(devc, HLIEL, 0, 0x0);
1119 emu10k_write_reg(devc, HLIEH, 0, 0x0);
1121 emu10k_write_reg(devc, CLIPL, 0, 0xffffffff);
1122 emu10k_write_reg(devc, CLIPH, 0, 0xffffffff);
1123 emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1124 emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1127 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1128 emu10k_write_reg(devc, SOC, 0, 0xf00); /* ?? */
1129 emu10k_write_reg(devc, AC97SLOT, 0, 0x3); /* ?? */
1133 emu10k_init_voice(devc, i);
1135 emu10k_write_reg(devc, SCS0, 0, 0x2109204);
1136 emu10k_write_reg(devc, SCS1, 0, 0x2109204);
1137 emu10k_write_reg(devc, SCS2, 0, 0x2109204);
1139 emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr);
1140 tmp = emu10k_read_reg(devc, PTBA, 0);
1142 emu10k_write_reg(devc, TCBA, 0, 0x0);
1143 emu10k_write_reg(devc, TCBS, 0, 0x4);
1146 if (devc->feature_mask & SB_71) {
1149 } else if (devc->feature_mask & SB_51) {
1152 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
1154 emu10k_write_reg(devc, AC97SLOT, 0, reg);
1156 if (devc->feature_mask & SB_AUDIGY2) {
1161 tmp = emu10k_read_reg(devc, EHC, 0);
1164 emu10k_write_reg(devc, EHC, 0, tmp);
1165 /* emu10k_write_reg (devc, SOC, 0, 0x00000000); */
1168 OUTL(devc, 0x600000, devc->regs + 0x20);
1169 OUTL(devc, 0x14, devc->regs + 0x24);
1172 OUTL(devc, 0x6E0000, devc->regs + 0x20);
1174 OUTL(devc, 0xFF00FF00, devc->regs + 0x24);
1177 tmp = INL(devc, devc->regs + HCFG);
1179 OUTL(devc, tmp, devc->regs + HCFG);
1186 tmp = INL(devc, devc->regs + 0x18);
1189 OUTL(devc, tmp, devc->regs + 0x18);
1192 if (devc->feature_mask & SB_AUDIGY2VAL) {
1197 tmp = emu10k_read_reg(devc, EHC, 0);
1200 emu10k_write_reg(devc, EHC, 0, tmp);
1203 OUTL(devc, 0x600000, devc->regs + 0x20);
1204 OUTL(devc, 0x14, devc->regs + 0x24);
1207 OUTL(devc, 0x7B0000, devc->regs + 0x20);
1208 OUTL(devc, 0xFF000000, devc->regs + 0x24);
1211 OUTL(devc, 0x7A0000, devc->regs + 0x20);
1212 OUTL(devc, 0xFF000000, devc->regs + 0x24);
1214 tmp = INL(devc, devc->regs + 0x18) & ~0x8;
1215 OUTL(devc, tmp, devc->regs + 0x18);
1218 emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1219 emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1221 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1224 if (devc->feature_mask & (SB_AUDIGY2|SB_AUDIGY2VAL))
1226 OUTL(devc,
1229 A_HCFG_AUTOMUTE | mode, devc->regs + HCFG);
1231 OUTL(devc, INL(devc, devc->regs + 0x18) |
1232 0x0004, devc->regs + 0x18); /* GPIO (S/PDIF enable) */
1236 tmp = INL(devc, devc->regs + 0x18);
1237 OUTL(devc, tmp | A_IOCFG_GPOUT2, devc->regs + 0x18);
1239 OUTL(devc, tmp | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2,
1240 devc->regs + 0x18);
1242 OUTL(devc, tmp, devc->regs + 0x18);
1244 OUTL(devc,
1246 HCFG_AUTOMUTE | HCFG_JOYENABLE, devc->regs + HCFG);
1251 tmp = INL(devc, devc->regs + HCFG);
1252 OUTL(devc, tmp | HCFG_GPOUT2, devc->regs + HCFG);
1254 OUTL(devc, tmp | HCFG_GPOUT1 | HCFG_GPOUT2, devc->regs + HCFG);
1256 OUTL(devc, tmp, devc->regs + HCFG);
1262 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1263 reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0;
1264 reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0);
1265 OUTL(devc, reg, devc->regs + 0x18);
1267 if (devc->feature_mask & SB_LIVE) { /* SBLIVE */
1268 reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0;
1269 reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0);
1270 OUTL(devc, reg, devc->regs + HCFG);
1273 if (devc->feature_mask & SB_AUDIGY2VAL) {
1274 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0060,
1275 devc->regs + 0x18);
1276 } else if (devc->feature_mask & SB_AUDIGY2) {
1277 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0040,
1278 devc->regs + 0x18);
1279 } else if (devc->feature_mask & SB_AUDIGY) {
1280 OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0080,
1281 devc->regs + 0x18);
1284 emu10k_init_effects(devc);
1322 emu10k_write_gpr(emu10k_devc_t *devc, int gpr, uint32_t value)
1325 devc->gpr_shadow[gpr].valid = B_TRUE;
1326 devc->gpr_shadow[gpr].value = value;
1327 emu10k_write_reg(devc, gpr + GPR0, 0, value);
1334 emu10k_devc_t *devc = ec->devc;
1345 mutex_enter(&devc->mutex);
1348 emu10k_write_gpr(devc, ec->gpr_num, left);
1349 emu10k_write_gpr(devc, ec->gpr_num + 1, right);
1351 mutex_exit(&devc->mutex);
1359 emu10k_devc_t *devc = ec->devc;
1367 mutex_enter(&devc->mutex);
1369 emu10k_write_gpr(devc, ec->gpr_num, v);
1370 mutex_exit(&devc->mutex);
1378 emu10k_devc_t *devc = ec->devc;
1380 mutex_enter(&devc->mutex);
1382 mutex_exit(&devc->mutex);
1414 emu10k_devc_t *devc = ec->devc;
1420 mutex_enter(&devc->mutex);
1426 mutex_exit(&devc->mutex);
1431 if (devc->feature_mask & SB_INVSP) {
1434 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1435 val = INL(devc, devc->regs + 0x18);
1438 OUTL(devc, val, devc->regs + 0x18);
1440 } else if (devc->feature_mask & SB_LIVE) {
1441 val = INL(devc, devc->regs + HCFG);
1444 OUTL(devc, val, devc->regs + HCFG);
1446 mutex_exit(&devc->mutex);
1454 emu10k_devc_t *devc = ec->devc;
1476 mutex_enter(&devc->mutex);
1479 emu10k_write_gpr(devc, GPR_REC_AC97, (set_val == INPUT_AC97));
1480 emu10k_write_gpr(devc, GPR_REC_SPDIF1, (set_val == INPUT_SPD1));
1481 emu10k_write_gpr(devc, GPR_REC_SPDIF2, (set_val == INPUT_SPD2));
1482 emu10k_write_gpr(devc, GPR_REC_DIGCD, (set_val == INPUT_DIGCD));
1483 emu10k_write_gpr(devc, GPR_REC_AUX2, (set_val == INPUT_AUX2));
1484 emu10k_write_gpr(devc, GPR_REC_LINE2, (set_val == INPUT_LINE2));
1485 emu10k_write_gpr(devc, GPR_REC_PCM, (set_val == INPUT_STEREOMIX));
1487 mutex_exit(&devc->mutex);
1493 emu10k_create_stereo(emu10k_devc_t *devc, int ctl, int gpr,
1501 ec = &devc->ctrls[ctl];
1502 ec->devc = devc;
1512 ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1515 mutex_enter(&devc->mutex);
1516 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval));
1517 emu10k_write_gpr(devc, gpr + 1, emu10k_convert_fixpoint(defval));
1518 mutex_exit(&devc->mutex);
1522 emu10k_create_mono(emu10k_devc_t *devc, int ctl, int gpr,
1530 ec = &devc->ctrls[ctl];
1531 ec->devc = devc;
1541 ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1544 mutex_enter(&devc->mutex);
1545 emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval));
1546 mutex_exit(&devc->mutex);
1559 emu10k_create_ac97src(emu10k_devc_t *devc)
1568 ec = &devc->ctrls[CTL_AC97SRC];
1572 ec->devc = devc;
1573 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC);
1597 ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1610 emu10k_create_recsrc(emu10k_devc_t *devc)
1618 ec = &devc->ctrls[CTL_RECSRC];
1625 ec->devc = devc;
1626 ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC);
1672 emu10k_write_gpr(devc, GPR_REC_SPDIF1, 0);
1673 emu10k_write_gpr(devc, GPR_REC_SPDIF2, 0);
1674 emu10k_write_gpr(devc, GPR_REC_DIGCD, 0);
1675 emu10k_write_gpr(devc, GPR_REC_AUX2, 0);
1676 emu10k_write_gpr(devc, GPR_REC_LINE2, 0);
1677 emu10k_write_gpr(devc, GPR_REC_PCM, 0);
1678 emu10k_write_gpr(devc, GPR_REC_AC97, 1);
1680 ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1685 emu10k_create_jack3(emu10k_devc_t *devc)
1692 ec = &devc->ctrls[CTL_JACK3];
1699 ec->devc = devc;
1705 ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1711 emu10k_create_controls(emu10k_devc_t *devc)
1716 emu10k_create_mono(devc, CTL_VOLUME, GPR_VOL_PCM,
1719 emu10k_create_stereo(devc, CTL_FRONT, GPR_VOL_FRONT,
1721 emu10k_create_stereo(devc, CTL_SURROUND, GPR_VOL_SURR,
1723 if (devc->feature_mask & (SB_51 | SB_71)) {
1724 emu10k_create_mono(devc, CTL_CENTER, GPR_VOL_CEN,
1726 emu10k_create_mono(devc, CTL_LFE, GPR_VOL_LFE,
1729 if (devc->feature_mask & SB_71) {
1730 emu10k_create_stereo(devc, CTL_SIDE, GPR_VOL_SIDE,
1734 emu10k_create_stereo(devc, CTL_RECGAIN, GPR_VOL_REC,
1737 emu10k_create_ac97src(devc);
1738 emu10k_create_recsrc(devc);
1744 if ((devc->feature_mask & SB_51) &&
1745 !(devc->feature_mask & SB_AUDIGY2VAL)) {
1746 emu10k_create_jack3(devc);
1750 ac97 = devc->ac97;
1770 emu10k_create_stereo(devc, CTL_AC97, GPR_MON_AC97,
1772 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1,
1774 emu10k_create_stereo(devc, CTL_DIGCD, GPR_MON_DIGCD,
1776 emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1,
1779 if ((devc->feature_mask & SB_NOEXP) == 0) {
1785 emu10k_create_stereo(devc, CTL_HEADPH, GPR_VOL_HEADPH,
1787 emu10k_create_stereo(devc, CTL_SPD2, GPR_MON_SPDIF2,
1789 emu10k_create_stereo(devc, CTL_LINE2, GPR_MON_LINE2,
1791 emu10k_create_stereo(devc, CTL_AUX2, GPR_MON_AUX2,
1797 emu10k_load_dsp(emu10k_devc_t *devc, uint32_t *code, int ncode,
1803 audio_dev_warn(devc->adev, "DSP file size too big");
1807 audio_dev_warn(devc->adev, "Too many inits");
1813 emu10k_write_efx(devc, UC0 + i, code[i]);
1818 emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]);
1823 emu10k_write_efx(devc, UC0 + (pc * 2), 0x10040); \
1824 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), 0x610040); \
1827 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 10) | y); \
1828 emu10k_write_efx(devc, UC0 + (pc * 2 + 1), (6 << 20) | (r << 10) | a); \
1832 emu10k_write_efx(devc, UC0 + (pc * 2), (x << 12) | y); \
1833 emu10k_write_efx(devc, UC0 + (pc * 2+1), (6 << 24) | (r << 12) | a); \
1838 emu10k_init_effects(emu10k_devc_t *devc)
1843 ASSERT(mutex_owned(&devc->mutex));
1845 if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1852 emu10k_write_efx(devc, GPR0 + i, 0);
1853 emu10k_write_reg(devc, AUDIGY_DBG, 0, 0);
1854 emu10k_load_dsp(devc,
1867 emu10k_write_efx(devc, GPR0 + i, 0);
1868 emu10k_write_reg(devc, DBG, 0, 0);
1869 emu10k_load_dsp(devc,
1928 emu10k_devc_t *devc;
1939 devc = kmem_zalloc(sizeof (*devc), KM_SLEEP);
1940 devc->dip = dip;
1941 ddi_set_driver_private(dip, devc);
1943 if ((devc->adev = audio_dev_alloc(dip, 0)) == NULL) {
1949 audio_dev_warn(devc->adev, "pci_config_setup failed");
1952 devc->pcih = pcih;
1961 if ((ddi_regs_map_setup(dip, 1, &devc->regs, 0, 0, &dev_attr,
1962 &devc->regsh)) != DDI_SUCCESS) {
1963 audio_dev_warn(devc->adev, "failed to map registers");
1993 audio_dev_warn(devc->adev, "Unrecognized device");
2006 devc->feature_mask = feature_mask;
2010 audio_dev_set_description(devc->adev, namebuf);
2011 audio_dev_set_version(devc->adev, model);
2013 mutex_init(&devc->mutex, NULL, MUTEX_DRIVER, 0);
2017 devc->max_mem = AUDIO_MEMSIZE;
2020 if (devc->max_mem > 32 * 1024 * 1024)
2021 devc->max_mem = 32 * 1024 * 1024;
2023 devc->max_pages = devc->max_mem / 4096;
2024 if (devc->max_pages < 1024)
2025 devc->max_pages = 1024;
2028 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
2029 &devc->pt_dmah) != DDI_SUCCESS) {
2030 audio_dev_warn(devc->adev,
2035 if (ddi_dma_mem_alloc(devc->pt_dmah, devc->max_pages * 4,
2037 &devc->pt_kaddr, &len, &devc->pt_acch) !=
2039 audio_dev_warn(devc->adev,
2044 if (ddi_dma_addr_bind_handle(devc->pt_dmah, NULL,
2045 devc->pt_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE,
2047 audio_dev_warn(devc->adev,
2052 devc->page_map = (void *)devc->pt_kaddr;
2053 devc->pt_paddr = cookie.dmac_address;
2054 bzero(devc->pt_kaddr, devc->max_pages * 4);
2057 if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
2058 &devc->silence_dmah) != DDI_SUCCESS) {
2059 audio_dev_warn(devc->adev,
2064 if (ddi_dma_mem_alloc(devc->silence_dmah, 4096,
2066 &devc->silence_kaddr, &len,
2067 &devc->silence_acch) != DDI_SUCCESS) {
2068 audio_dev_warn(devc->adev,
2073 (void) ddi_dma_sync(devc->silence_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
2075 if (ddi_dma_addr_bind_handle(devc->silence_dmah, NULL,
2076 devc->silence_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE,
2078 audio_dev_warn(devc->adev,
2083 devc->silence_paddr = cookie.dmac_address;
2084 bzero(devc->silence_kaddr, 4096);
2085 devc->audio_memptr = 4096; /* Skip the silence page */
2087 for (i = 0; i < devc->max_pages; i++)
2088 FILL_PAGE_MAP_ENTRY(i, devc->silence_paddr);
2090 (void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
2092 devc->ac97 = ac97_allocate(devc->adev, dip,
2093 emu10k_read_ac97, emu10k_write_ac97, devc);
2094 if (devc->ac97 == NULL) {
2095 audio_dev_warn(devc->adev, "failed to allocate ac97 handle");
2099 ac97_probe_controls(devc->ac97);
2102 if (emu10k_alloc_port(devc, EMU10K_REC) != DDI_SUCCESS)
2105 if (emu10k_alloc_port(devc, EMU10K_PLAY) != DDI_SUCCESS)
2109 mutex_enter(&devc->mutex);
2110 if (emu10k_hwinit(devc) != DDI_SUCCESS) {
2111 mutex_exit(&devc->mutex);
2114 mutex_exit(&devc->mutex);
2116 emu10k_create_controls(devc);
2118 if (audio_dev_register(devc->adev) != DDI_SUCCESS) {
2119 audio_dev_warn(devc->adev, "unable to register audio device");
2128 emu10k_destroy(devc);
2135 emu10k_devc_t *devc;
2137 devc = ddi_get_driver_private(dip);
2139 mutex_enter(&devc->mutex);
2140 if (emu10k_hwinit(devc) != DDI_SUCCESS) {
2141 mutex_exit(&devc->mutex);
2147 audio_dev_warn(devc->adev, "FAILED to RESUME device");
2151 mutex_exit(&devc->mutex);
2154 ac97_reset(devc->ac97);
2156 audio_dev_resume(devc->adev);
2162 emu10k_detach(emu10k_devc_t *devc)
2164 if (audio_dev_unregister(devc->adev) != DDI_SUCCESS)
2167 emu10k_destroy(devc);
2172 emu10k_suspend(emu10k_devc_t *devc)
2174 audio_dev_suspend(devc->adev);
2256 emu10k_devc_t *devc;
2258 devc = ddi_get_driver_private(dip);
2262 return (emu10k_detach(devc));
2265 return (emu10k_suspend(devc));
2275 emu10k_devc_t *devc;
2277 devc = ddi_get_driver_private(dip);
2281 emu10k_write_reg(devc, VEDS, i, 0);
2284 emu10k_write_reg(devc, VTFT, i, 0);
2285 emu10k_write_reg(devc, CVCF, i, 0);
2286 emu10k_write_reg(devc, PTAB, i, 0);
2287 emu10k_write_reg(devc, CPF, i, 0);
2293 OUTL(devc,
2295 HCFG_MUTEBUTTONENABLE, devc->regs + HCFG);
2298 emu10k_write_reg(devc, ADCSR, 0, 0x0);
2299 emu10k_write_reg(devc, ADCBA, 0, 0x0);
2300 emu10k_write_reg(devc, ADCBA, 0, 0x0);
2302 emu10k_write_reg(devc, PTBA, 0, 0);