Lines Matching refs:uvp
60 static int hci1394_ixl_update_prepare(hci1394_ixl_update_vars_t *uvp);
61 static int hci1394_ixl_update_prep_jump(hci1394_ixl_update_vars_t *uvp);
62 static int hci1394_ixl_update_prep_set_skipmode(hci1394_ixl_update_vars_t *uvp);
63 static int hci1394_ixl_update_prep_set_tagsync(hci1394_ixl_update_vars_t *uvp);
64 static int hci1394_ixl_update_prep_recv_pkt(hci1394_ixl_update_vars_t *uvp);
65 static int hci1394_ixl_update_prep_recv_buf(hci1394_ixl_update_vars_t *uvp);
66 static int hci1394_ixl_update_prep_send_pkt(hci1394_ixl_update_vars_t *uvp);
67 static int hci1394_ixl_update_prep_send_buf(hci1394_ixl_update_vars_t *uvp);
68 static int hci1394_ixl_update_perform(hci1394_ixl_update_vars_t *uvp);
69 static int hci1394_ixl_update_evaluate(hci1394_ixl_update_vars_t *uvp);
70 static int hci1394_ixl_update_analysis(hci1394_ixl_update_vars_t *uvp);
71 static void hci1394_ixl_update_set_locn_info(hci1394_ixl_update_vars_t *uvp);
72 static int hci1394_ixl_update_enable(hci1394_ixl_update_vars_t *uvp);
73 static int hci1394_ixl_update_endup(hci1394_ixl_update_vars_t *uvp);
274 hci1394_ixl_update_enable(hci1394_ixl_update_vars_t *uvp)
292 ASSERT(MUTEX_NOT_HELD(&uvp->ctxtp->intrprocmutex));
293 mutex_enter(&uvp->ctxtp->intrprocmutex);
300 if (uvp->ctxtp->intr_flags & HCI1394_ISO_CTXT_INUPDATE) {
301 uvp->upd_status = IXL1394_EUPDATE_DISALLOWED;
303 } else if (uvp->ctxtp->intr_flags & HCI1394_ISO_CTXT_ININTR) {
312 uvp->upd_status = IXL1394_EUPDATE_DISALLOWED;
321 mutex_exit(&uvp->ctxtp->intrprocmutex);
323 mutex_enter(&uvp->ctxtp->intrprocmutex);
326 } else if (uvp->ctxtp->intr_flags & HCI1394_ISO_CTXT_INCALL) {
327 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
334 uvp->ctxtp->intr_flags |= HCI1394_ISO_CTXT_INUPDATE;
337 ASSERT(MUTEX_HELD(&uvp->ctxtp->intrprocmutex));
338 mutex_exit(&uvp->ctxtp->intrprocmutex);
352 hci1394_ixl_update_endup(hci1394_ixl_update_vars_t *uvp)
361 ctxtp = uvp->ctxtp;
380 status = hci1394_ixl_dma_sync(uvp->soft_statep, ctxtp);
388 mutex_enter(&uvp->ctxtp->intrprocmutex);
390 mutex_exit(&uvp->ctxtp->intrprocmutex);
395 ASSERT(MUTEX_NOT_HELD(&uvp->ctxtp->intrprocmutex));
396 mutex_enter(&uvp->ctxtp->intrprocmutex);
400 mutex_exit(&uvp->ctxtp->intrprocmutex);
405 hci1394_do_stop(uvp->soft_statep, ctxtp, B_TRUE, ID1394_DONE);
407 hci1394_do_stop(uvp->soft_statep, ctxtp, B_TRUE, ID1394_FAIL);
417 * Preparation for the actual update (using temp uvp struct)
420 hci1394_ixl_update_prepare(hci1394_ixl_update_vars_t *uvp)
428 if (uvp->ixlnewp->ixl_opcode != uvp->ixloldp->ixl_opcode) {
430 uvp->upd_status = IXL1394_EOPCODE_MISMATCH;
442 switch (uvp->ixl_opcode) {
448 old_callback_ixlp = (ixl1394_callback_t *)uvp->ixloldp;
449 new_callback_ixlp = (ixl1394_callback_t *)uvp->ixlnewp;
463 ret = hci1394_ixl_update_prep_jump(uvp);
470 ret = hci1394_ixl_update_prep_set_skipmode(uvp);
477 ret = hci1394_ixl_update_prep_set_tagsync(uvp);
485 ret = hci1394_ixl_update_prep_recv_pkt(uvp);
492 ret = hci1394_ixl_update_prep_recv_buf(uvp);
501 ret = hci1394_ixl_update_prep_send_pkt(uvp);
508 ret = hci1394_ixl_update_prep_send_buf(uvp);
516 uvp->upd_status = IXL1394_EOPCODE_DISALLOWED;
529 hci1394_ixl_update_prep_jump(hci1394_ixl_update_vars_t *uvp)
545 old_jump_ixlp = (ixl1394_jump_t *)uvp->ixloldp;
546 new_jump_ixlp = (ixl1394_jump_t *)uvp->ixlnewp;
562 uvp->upd_status = IXL1394_EJUMP_NOT_TO_LABEL;
583 uvp->jumpaddr = ((hci1394_xfer_ctl_t *)
591 if ((uvp->ixlxferp = (ixl1394_command_t *)
595 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
608 xferctlp = (hci1394_xfer_ctl_t *)uvp->ixlxferp->compiler_privatep;
617 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
626 uvp->hcihdr = desc_hdr & ~DESC_INTR_ENBL;
629 uvp->ixldepth = xferctlp->cnt - 1;
630 uvp->ixlcount = 1;
640 uvp->hcihdr |= DESC_INTR_ENBL;
645 uvp->hcihdr |= DESC_INTR_ENBL;
650 * IXL1394_SKIP_TO_NEXT then set uvp->skipmode to IXL1394_SKIP_TO_NEXT
651 * and set uvp->skipxferp to uvp->jumpaddr and set uvp->hci_offset to
658 uvp->skipmode = IXL1394_SKIP_TO_STOP;
659 if ((uvp->ixlxferp->ixl_opcode & IXL1394_OPF_ONXMIT) != 0) {
663 (uvp->ctxtp->default_skipmode == IXL1394_OPF_ONXMIT)) {
665 uvp->skipmode = IXL1394_SKIP_TO_NEXT;
666 uvp->skipaddr = uvp->jumpaddr;
674 if (uvp->ixlxferp->ixl_opcode ==
680 uvp->hci_offset -= 2;
686 uvp->hci_offset -= 1;
700 hci1394_ixl_update_prep_set_skipmode(hci1394_ixl_update_vars_t *uvp)
710 old_set_skipmode_ixlp = (ixl1394_set_skipmode_t *)uvp->ixloldp;
711 new_set_skipmode_ixlp = (ixl1394_set_skipmode_t *)uvp->ixlnewp;
732 uvp->ixlxferp = uvp->ixloldp->next_ixlp;
733 while ((uvp->ixlxferp != NULL) && (((uvp->ixlxferp->ixl_opcode &
735 ((uvp->ixlxferp->ixl_opcode & IXL1394_OPTY_MASK) != 0))) {
737 uvp->ixlxferp = uvp->ixlxferp->next_ixlp;
741 if (uvp->ixlxferp == NULL) {
743 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
756 uvp->ixlxferp->compiler_privatep) == NULL) {
758 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
765 uvp->hci_offset = xferctlp->dma[0].dma_bound & DESC_Z_MASK;
772 if (uvp->ixlxferp->ixl_opcode == IXL1394_OP_SEND_HDR_ONLY) {
777 uvp->hci_offset -= 2;
783 uvp->hci_offset -= 1;
787 uvp->ixldepth = 0;
788 uvp->ixlcount = xferctlp->cnt;
791 uvp->skipmode = new_set_skipmode_ixlp->skipmode;
793 if ((uvp->skipmode != IXL1394_SKIP_TO_NEXT) &&
794 (uvp->skipmode != IXL1394_SKIP_TO_SELF) &&
795 (uvp->skipmode != IXL1394_SKIP_TO_STOP) &&
796 (uvp->skipmode != IXL1394_SKIP_TO_LABEL)) {
799 uvp->upd_status = IXL1394_EBAD_SKIPMODE;
808 if (uvp->skipmode == IXL1394_SKIP_TO_LABEL) {
816 uvp->upd_status = IXL1394_EBAD_SKIP_LABEL;
835 if ((uvp->skipxferp = ixlp) != NULL) {
842 uvp->skipaddr = xferctlp->dma[0].dma_bound;
849 if (uvp->skipmode == IXL1394_SKIP_TO_NEXT) {
851 (void) hci1394_ixl_find_next_exec_xfer(uvp->ixlxferp->next_ixlp,
865 uvp->skipaddr = xferctlp->dma[0].dma_bound;
878 hci1394_ixl_update_prep_set_tagsync(hci1394_ixl_update_vars_t *uvp)
887 old_set_tagsync_ixlp = (ixl1394_set_tagsync_t *)uvp->ixloldp;
888 new_set_tagsync_ixlp = (ixl1394_set_tagsync_t *)uvp->ixlnewp;
902 uvp->ixlxferp = uvp->ixloldp->next_ixlp;
903 while ((uvp->ixlxferp != NULL) && (((uvp->ixlxferp->ixl_opcode &
905 ((uvp->ixlxferp->ixl_opcode & IXL1394_OPTY_MASK) != 0))) {
907 uvp->ixlxferp = uvp->ixlxferp->next_ixlp;
911 if (uvp->ixlxferp == NULL) {
913 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
921 if (uvp->ixlxferp->ixl_opcode == IXL1394_OP_SEND_NO_PKT) {
930 uvp->pkthdr1 = (uvp->ctxtp->isospd << DESC_PKT_SPD_SHIFT) |
932 (uvp->ctxtp->isochan << DESC_PKT_CHAN_SHIFT) |
940 uvp->ixlxferp->compiler_privatep) == NULL) {
942 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
948 uvp->hdr_offset = xferctlp->dma[0].dma_bound & DESC_Z_MASK;
955 if (uvp->ixlxferp->ixl_opcode == IXL1394_OP_SEND_HDR_ONLY) {
960 uvp->hdr_offset = 0;
966 uvp->hdr_offset -= 1;
970 uvp->ixldepth = 0;
971 uvp->ixlcount = xferctlp->cnt;
984 hci1394_ixl_update_prep_recv_pkt(hci1394_ixl_update_vars_t *uvp)
998 old_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixloldp;
999 new_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixlnewp;
1018 uvp->upd_status = IXL1394_EXFER_BUF_MISSING;
1026 if (uvp->ixl_opcode == IXL1394_OP_RECV_PKT_U) {
1031 uvp->ixlxferp = (ixl1394_command_t *)
1032 uvp->ixloldp->compiler_privatep;
1034 if (uvp->ixlxferp == NULL) {
1037 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1045 uvp->ixlxferp = uvp->ixloldp;
1050 uvp->ixlxferp->compiler_privatep) == NULL) {
1053 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1061 uvp->ixldepth = 0;
1062 uvp->ixlcount = 1;
1068 uvp->hci_offset = xferctlp->dma[0].dma_bound & DESC_Z_MASK;
1074 uvp->hci_offset -= (1 + uvp->ixloldp->compiler_resv);
1080 uvp->bufsize = ((ixl1394_xfer_pkt_t *)uvp->ixlnewp)->size;
1081 uvp->bufaddr = ((ixl1394_xfer_pkt_t *)
1082 uvp->ixlnewp)->ixl_buf.ixldmac_addr;
1089 uvp->hci_offset;
1097 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1106 uvp->hcihdr = desc_hdr;
1107 uvp->hcihdr &= ~DESC_HDR_REQCOUNT_MASK;
1108 uvp->hcihdr |= (uvp->bufsize << DESC_HDR_REQCOUNT_SHIFT) &
1110 uvp->hcistatus = (uvp->bufsize << DESC_ST_RESCOUNT_SHIFT) &
1123 hci1394_ixl_update_prep_recv_buf(hci1394_ixl_update_vars_t *uvp)
1132 old_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixloldp;
1133 new_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixlnewp;
1141 if (((uvp->ctxtp->ctxt_flags & HCI1394_ISO_CTXT_BFFILL) != 0) ||
1157 uvp->upd_status = IXL1394_EXFER_BUF_MISSING;
1169 if ((uvp->ctxtp->ctxt_flags & HCI1394_ISO_CTXT_BFFILL) == 0) {
1175 uvp->upd_status = IXL1394_EXFER_BUF_CNT_DIFF;
1185 uvp->ixlxferp = uvp->ixloldp;
1188 if ((xferctlp = (hci1394_xfer_ctl_t *)uvp->ixlxferp->compiler_privatep)
1192 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1200 uvp->ixldepth = 0;
1201 uvp->ixlcount = xferctlp->cnt;
1204 if ((uvp->ctxtp->ctxt_flags & HCI1394_ISO_CTXT_BFFILL) == 0) {
1205 uvp->bufsize = new_xfer_buf_ixlp->pkt_size;
1207 uvp->bufsize = new_xfer_buf_ixlp->size;
1211 uvp->bufaddr = new_xfer_buf_ixlp->ixl_buf.ixldmac_addr;
1214 uvp->hci_offset = 0;
1215 uvp->hcihdr = (uvp->bufsize << DESC_HDR_REQCOUNT_SHIFT) &
1217 uvp->hcistatus = (uvp->bufsize << DESC_ST_RESCOUNT_SHIFT) &
1232 hci1394_ixl_update_prep_send_pkt(hci1394_ixl_update_vars_t *uvp)
1246 old_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixloldp;
1247 new_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixlnewp;
1266 uvp->upd_status = IXL1394_EXFER_BUF_MISSING;
1274 if ((uvp->ixl_opcode == IXL1394_OP_SEND_PKT_WHDR_ST_U) &&
1277 uvp->upd_status = IXL1394_EPKT_HDR_MISSING;
1285 if (uvp->ixl_opcode == IXL1394_OP_SEND_PKT_U) {
1290 uvp->ixlxferp = (ixl1394_command_t *)
1293 if (uvp->ixlxferp == NULL) {
1295 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1303 uvp->ixlxferp = uvp->ixloldp;
1312 uvp->ixlxferp->compiler_privatep) == NULL) {
1314 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1322 uvp->ixldepth = 0;
1323 uvp->ixlcount = 1;
1329 uvp->hdr_offset = xferctlp->dma[0].dma_bound & DESC_Z_MASK - 1;
1335 uvp->hci_offset = uvp->hdr_offset - 2 - uvp->ixloldp->compiler_resv;
1338 uvp->bufsize = new_xfer_pkt_ixlp->size;
1339 uvp->bufaddr = new_xfer_pkt_ixlp->ixl_buf.ixldmac_addr;
1345 if (uvp->ixl_opcode == IXL1394_OP_SEND_PKT_WHDR_ST_U) {
1346 uvp->bufsize -= 4;
1347 uvp->bufaddr += 4;
1352 uvp->hci_offset;
1360 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1369 uvp->hcihdr = desc_hdr;
1370 uvp->hcihdr &= ~DESC_HDR_REQCOUNT_MASK;
1371 uvp->hcihdr |= (uvp->bufsize << DESC_HDR_REQCOUNT_SHIFT) &
1376 uvp->pkthdr2 = desc_hdr2;
1377 uvp->pkthdr2 = (uvp->pkthdr2 & DESC_PKT_DATALEN_MASK) >>
1379 uvp->pkthdr2 -= old_xfer_pkt_ixlp->size;
1380 uvp->pkthdr2 += uvp->bufsize;
1382 if (uvp->pkthdr2 > 0xFFFF) {
1383 uvp->upd_status = IXL1394_EPKTSIZE_MAX_OFLO;
1389 uvp->pkthdr2 = (uvp->pkthdr2 << DESC_PKT_DATALEN_SHIFT) &
1402 hci1394_ixl_update_prep_send_buf(hci1394_ixl_update_vars_t *uvp)
1411 old_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixloldp;
1412 new_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixlnewp;
1432 uvp->upd_status = IXL1394_EXFER_BUF_MISSING;
1448 uvp->upd_status = IXL1394_EXFER_BUF_CNT_DIFF;
1456 uvp->ixlxferp = uvp->ixloldp;
1464 uvp->ixlxferp->compiler_privatep) == NULL) {
1466 uvp->upd_status = IXL1394_EORIG_IXL_CORRUPTED;
1474 uvp->ixldepth = 0;
1475 uvp->ixlcount = xferctlp->cnt;
1481 uvp->hdr_offset = xferctlp->dma[0].dma_bound & DESC_Z_MASK - 1;
1484 uvp->hci_offset = 0;
1487 uvp->bufsize = new_xfer_buf_ixlp->pkt_size;
1488 uvp->bufaddr = new_xfer_buf_ixlp->ixl_buf.ixldmac_addr;
1494 if (uvp->ixl_opcode == IXL1394_OP_SEND_PKT_WHDR_ST_U) {
1495 uvp->bufsize -= 4;
1496 uvp->bufaddr += 4;
1500 uvp->hcihdr = (uvp->bufsize << DESC_HDR_REQCOUNT_SHIFT) &
1504 uvp->pkthdr2 = (uvp->bufsize << DESC_PKT_DATALEN_SHIFT) &
1517 hci1394_ixl_update_perform(hci1394_ixl_update_vars_t *uvp)
1531 ctxtp = uvp->ctxtp;
1537 if ((uvp->ixlxferp == NULL) ||
1539 uvp->ixlxferp->compiler_privatep) == NULL)) {
1541 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1550 switch (uvp->ixl_opcode) {
1556 old_jump_ixlp = (ixl1394_jump_t *)uvp->ixloldp;
1557 new_jump_ixlp = (ixl1394_jump_t *)uvp->ixlnewp;
1570 ddi_put32(acc_hdl, &hcidescp->hdr, uvp->hcihdr);
1571 ddi_put32(acc_hdl, &hcidescp->branch, uvp->jumpaddr);
1578 if (uvp->skipmode == IXL1394_SKIP_TO_NEXT) {
1579 hcidescp -= uvp->hci_offset;
1580 ddi_put32(acc_hdl, &hcidescp->branch, uvp->skipaddr);
1587 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1602 old_set_skipmode_ixlp = (ixl1394_set_skipmode_t *)uvp->ixloldp;
1603 new_set_skipmode_ixlp = (ixl1394_set_skipmode_t *)uvp->ixlnewp;
1609 if (uvp->skipmode == IXL1394_SKIP_TO_NEXT) {
1610 skipaddrlast = uvp->skipaddr;
1621 xferctlp->dma[ii].dma_descp - uvp->hci_offset;
1625 if (uvp->skipmode == IXL1394_SKIP_TO_NEXT) {
1627 uvp->skipaddr =
1630 uvp->skipaddr = skipaddrlast;
1632 } else if (uvp->skipmode == IXL1394_SKIP_TO_SELF) {
1633 uvp->skipaddr = xferctlp->dma[ii].dma_bound;
1636 ddi_put32(acc_hdl, &hcidescp->branch, uvp->skipaddr);
1642 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1654 * uvp->skipxferp
1656 old_set_skipmode_ixlp->skipmode = uvp->skipmode;
1659 (ixl1394_priv_t)uvp->skipxferp;
1666 old_set_tagsync_ixlp = (ixl1394_set_tagsync_t *)uvp->ixloldp;
1667 new_set_tagsync_ixlp = (ixl1394_set_tagsync_t *)uvp->ixlnewp;
1677 xferctlp->dma[ii].dma_descp - uvp->hdr_offset;
1680 ddi_put32(acc_hdl, &hcidescp->q1, uvp->pkthdr1);
1686 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1709 old_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixloldp;
1710 new_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixlnewp;
1717 xferctlp->dma[0].dma_descp - uvp->hci_offset;
1720 ddi_put32(acc_hdl, &hcidescp->hdr, uvp->hcihdr);
1721 ddi_put32(acc_hdl, &hcidescp->data_addr, uvp->bufaddr);
1727 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1737 uvp->hcistatus;
1744 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1767 old_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixloldp;
1768 new_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixlnewp;
1778 xferctlp->dma[ii].dma_descp - uvp->hci_offset;
1782 ddi_put32(acc_hdl, &hcidescp->data_addr, uvp->bufaddr);
1788 uvp->bufaddr += uvp->bufsize;
1794 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1808 uvp->hcihdr;
1817 uvp->hcistatus;
1824 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1850 old_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixloldp;
1851 new_xfer_pkt_ixlp = (ixl1394_xfer_pkt_t *)uvp->ixlnewp;
1859 uvp->hdr_offset;
1863 ddi_put32(acc_hdl, &hcidescp->q2, uvp->pkthdr2);
1864 ddi_put32(acc_hdl, &hcidescp->hdr, uvp->hcihdr);
1865 ddi_put32(acc_hdl, &hcidescp->data_addr, uvp->bufaddr);
1871 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1893 old_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixloldp;
1894 new_xfer_buf_ixlp = (ixl1394_xfer_buf_t *)uvp->ixlnewp;
1905 xferctlp->dma[ii].dma_descp - uvp->hdr_offset;
1909 ddi_put32(acc_hdl, &hcidescp->q2, uvp->pkthdr2);
1910 ddi_put32(acc_hdl, &hcidescp->data_addr, uvp->bufaddr);
1913 uvp->bufaddr += uvp->bufsize;
1919 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1933 uvp->hcihdr;
1940 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1962 uvp->upd_status = IXL1394_EINTERNAL_ERROR;
1971 HCI1394_IRCTXT_CTRL_SET(uvp->soft_statep, ctxtp->ctxt_index,
1974 HCI1394_ITCTXT_CTRL_SET(uvp->soft_statep, ctxtp->ctxt_index,
1990 hci1394_ixl_update_evaluate(hci1394_ixl_update_vars_t *uvp)
2000 ctxtp = uvp->ctxtp;
2033 if (hci1394_ixl_dma_sync(uvp->soft_statep, ctxtp) ==
2037 uvp->upd_status = IXL1394_EPOST_UPD_DMALOST;
2051 if ((uvp->locn_info[ii].ixlp == ixlp) &&
2052 (uvp->locn_info[ii].ixldepth == ixldepth)) {
2065 uvp->upd_status = IXL1394_EPOST_UPD_DMALOST;
2078 hci1394_ixl_update_analysis(hci1394_ixl_update_vars_t *uvp)
2089 ctxtp = uvp->ctxtp;
2123 status = hci1394_ixl_dma_sync(uvp->soft_statep, ctxtp);
2129 uvp->upd_status = IXL1394_EPRE_UPD_DMALOST;
2141 hci1394_ixl_update_set_locn_info(uvp);
2154 if ((uvp->locn_info[ii].ixlp == uvp->ixlxferp) &&
2155 (uvp->locn_info[ii].ixldepth >= uvp->ixldepth) &&
2156 (uvp->locn_info[ii].ixldepth <
2157 (uvp->ixldepth + uvp->ixlcount))) {
2159 uvp->upd_status = IXL1394_ERISK_PROHIBITS_UPD;
2179 hci1394_ixl_update_set_locn_info(hci1394_ixl_update_vars_t *uvp)
2193 ctxtp = uvp->ctxtp;
2211 uvp->locn_info[ii].ixlp = ixlp;
2212 uvp->locn_info[ii].ixldepth = ixldepth;