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4 * for Intel AES-NI instructions. Rights for redistribution and usage
5 * in source and binary forms are granted according to the OpenSSL
14 * of Intel processor, as of 2009. These instructions enable fast and
15 * secure data encryption and decryption, using the Advanced Encryption
19 * encryption and decryption, and the other two instructions support
28 * Redistribution and use in source and binary forms, with or without
33 * notice, this list of conditions and the following disclaimer.
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
45 * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
78 * This source originates as files aes-intel.S and eng_aesni_asm.pl, in
79 * patches sent sent Dec. 9, 2008 and Dec. 24, 2008, respectively, by
87 * and EXPORT DELETE END markers, and dummy C function definitions for lint.
89 * 2. Formatted code, added comments, and added #includes and #defines.
91 * 3. If bit CR0.TS is set, clear and set the TS bit, after and before
92 * calling kpreempt_disable() and kpreempt_enable().
93 * If the TS bit is not set, Save and restore %xmm registers at the beginning
94 * and end of function calls (%xmm* registers are not saved and restored by
97 * 4. Renamed functions, reordered parameters, and changed return value
144 * ct is crypto text, and MAX_AES_NR is 14.
195 * The CLTS and STTS macros push and pop P1 (%rdi) already.
213 and $-XMM_ALIGN, %rsp; \
223 * If CR0_TS was not set above, pop %xmm0 and %xmm1 off stack,
239 * If CR0_TS is not set, align stack (with push %rbp) and push
248 and $-XMM_ALIGN, %rsp; \
390 * Clear and set the CR0.TS bit on entry and exit, respectively, if TS is set
391 * on entry. Otherwise, if TS is not set, save and restore %xmm registers
594 * Clear and set the CR0.TS bit on entry and exit, respectively, if TS is set
595 * on entry. Otherwise, if TS is not set, save and restore %xmm registers
670 * Encrypt a single block (in and out can overlap).
674 * Clear and set the CR0.TS bit on entry and exit, respectively, if TS is set
675 * on entry. Otherwise, if TS is not set, save and restore %xmm registers
741 / AES 192 and 256
749 / AES 128, 192, and 256
780 * Decrypt a single block (in and out can overlap).
784 * Clear and set the CR0.TS bit on entry and exit, respectively, if TS is set
785 * on entry. Otherwise, if TS is not set, save and restore %xmm registers
828 / AES 192 and 256
836 / AES 128, 192, and 256