x86/vm/sharedRuntime_x86_32.cpp

225   // will allow deoptimization at this safepoint to find all possible
422   //       On Intel we have to round all doubles (and most floats) at
575   // at all.  We've come from compiled code and are attempting to jump to the
844         // are accessed as negative so LSW is at LOW address
856         // are accessed as negative so LSW is at LOW address
1441     member_reg = rbx;  // known to be free at this point
1472       receiver_reg = rcx;  // known to be free at this point
1530     int stack_slots = SharedRuntime::out_preserve_stack_slots();  // no out slots at all, actually
1597         const char* at = atype->as_C_string();
1598         if (strlen(at) == 2) {
1599           assert(at[0] == '[', "must be");
1600           switch (at[1]) {
1758   // if we align at 8 then we will be sure 5 bytes are in the same line
1772   // The instruction at the verified entry point must be 5 bytes or longer
1852   // We ignore the extra arguments during the shuffle and handle them at the
1873   // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
1944   // We have all of the arguments setup at this point. We must not touch any register
1945   // argument registers at this point (what if we save/restore them there are no oop?
2449   // already been captured in the vframeArray at the time the return PC was
2466   // return address is the pc describes what bci to do re-execute at
2478   // all registers are dead at this entry point, except for rax, and
2494   // tos: stack at point of call to method that threw the exception (i.e. only
2593   // deopt at a poll point with the non standard control word. However, we should make
2614   // sp should be pointing at the return address to the caller (3)
2840   // sp should be pointing at the return address to the caller (3)
2969   // If cause_return is true we are at a poll_return and there is
3000   // will allow deoptimization at this safepoint to find all possible
3040 // of a java call. All the argument registers are live at this point