Lines Matching defs:rn
611 void MacroAssembler::add_slow(Register rd, Register rn, int c) {
614 if (rd != rn) {
615 mov(rd, rn);
620 sub_slow(rd, rn, -c);
624 guarantee(rd != rn, "no large add_slow with only one register");
626 add(rd, rn, rd);
631 add(rd, rn, lo, lsl0);
634 add(rd, (lo == 0) ? rn : rd, hi, lsl12);
640 return sub(rd, rn, (-c));
644 add(rd, rn, low);
645 rn = rd;
649 add(rd, rn, c & ~0x3fc);
650 } else if (rd != rn) {
652 mov(rd, rn); // need to generate at least one move!
657 void MacroAssembler::sub_slow(Register rd, Register rn, int c) {
660 add_slow(rd, rn, -c);
664 guarantee(rd != rn, "no large sub_slow with only one register");
666 sub(rd, rn, rd);
671 sub(rd, rn, lo, lsl0);
674 sub(rd, (lo == 0) ? rn : rd, hi, lsl12);
680 return add(rd, rn, (-c));
684 sub(rd, rn, low);
685 rn = rd;
689 sub(rd, rn, c & ~0x3fc);
690 } else if (rd != rn) {
692 mov(rd, rn); // need to generate at least one move!
1005 void MacroAssembler::zero_extend(Register rd, Register rn, int bits) {
1008 case 8: uxtb(rd, rn); break;
1009 case 16: uxth(rd, rn); break;
1010 case 32: mov_w(rd, rn); break;
1015 andr(rd, rn, (1 << bits) - 1);
1017 bic(rd, rn, -1 << bits);
1019 mov(rd, AsmOperand(rn, lsl, 32 - bits));
1025 void MacroAssembler::sign_extend(Register rd, Register rn, int bits) {
1028 case 8: sxtb(rd, rn); break;
1029 case 16: sxth(rd, rn); break;
1030 case 32: sxtw(rd, rn); break;
1034 mov(rd, AsmOperand(rn, lsl, 32 - bits));