Lines Matching defs:rn
251 void mnemonic(Register rt, Register rn) { \
253 o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr()); \
276 void mnemonic(Register rs, Register rt, Register rn) { \
278 assert (rs != rn, "should be different"); \
280 o0 << 15 | 0b11111 << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr()); \
294 void mnemonic(Register rt, Register rt2, Register rn) { \
297 o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr()); \
307 void mnemonic(Register rs, Register rt, Register rt2, Register rn) { \
310 assert (rs != rn, "should be different"); \
312 o0 << 15 | rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr()); \
322 void mnemonic(Register rt, Register rt2, Register rn, int offset = 0) { \
327 rt2->encoding_with_zr() << 10 | rn->encoding_with_sp() << 5 | rt->encoding_with_zr()); \
337 void mnemonic(FloatRegister rt, FloatRegister rt2, Register rn, int offset = 0) { \
342 rt2->encoding() << 10 | rn->encoding_with_sp() << 5 | rt->encoding()); \
495 void mnemonic(Register rd, Register rn, const LogicalImmediate& imm) { \
499 imm.imms() << 10 | rn->encoding_with_zr() << 5 | \
502 void mnemonic(Register rd, Register rn, uintx imm) { \
504 mnemonic(rd, rn, limm); \
506 void mnemonic(Register rd, Register rn, unsigned int imm) { \
507 mnemonic(rd, rn, (uintx)imm); \
521 void tst(Register rn, unsigned int imm) {
522 ands(ZR, rn, imm);
525 void tst_w(Register rn, unsigned int imm) {
526 ands_w(ZR, rn, imm);
530 void mnemonic(Register rd, Register rn, AsmOperand operand) { \
534 rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
556 void tst(Register rn, AsmOperand operand) {
557 ands(ZR, rn, operand);
560 void tst_w(Register rn, AsmOperand operand) {
561 ands_w(ZR, rn, operand);
573 void mnemonic(Register rd, Register rn, const ArithmeticImmediate& imm) { \
576 imm.imm() << 10 | rn->encoding_with_sp() << 5 | \
579 void mnemonic(Register rd, Register rn, int imm) { \
580 mnemonic(rd, rn, ArithmeticImmediate(imm)); \
582 void mnemonic(Register rd, Register rn, int imm, AsmShift12 shift) { \
583 mnemonic(rd, rn, ArithmeticImmediate(imm, shift)); \
585 void mnemonic(Register rd, Register rn, Register rm, AsmExtendOp extend, int shift_imm = 0) { \
588 extend << 13 | shift_imm << 10 | rn->encoding_with_sp() << 5 | \
591 void mnemonic(Register rd, Register rn, AsmOperand operand) { \
596 rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
626 void cmp(Register rn, int imm) {
627 subs(ZR, rn, imm);
630 void cmp_w(Register rn, int imm) {
631 subs_w(ZR, rn, imm);
634 void cmp(Register rn, Register rm) {
636 if (rn == SP) {
637 subs(ZR, rn, rm, ex_uxtx);
639 subs(ZR, rn, rm);
643 void cmp_w(Register rn, Register rm) {
644 assert ((rn != SP) && (rm != SP), "SP should not be used in 32-bit cmp");
645 subs_w(ZR, rn, rm);
648 void cmp(Register rn, AsmOperand operand) {
649 assert (rn != SP, "SP is not allowed in cmp with shifted register (AsmOperand)");
650 subs(ZR, rn, operand);
653 void cmn(Register rn, int imm) {
654 adds(ZR, rn, imm);
657 void cmn_w(Register rn, int imm) {
658 adds_w(ZR, rn, imm);
661 void cmn(Register rn, Register rm) {
663 if (rn == SP) {
664 adds(ZR, rn, rm, ex_uxtx);
666 adds(ZR, rn, rm);
670 void cmn_w(Register rn, Register rm) {
671 assert ((rn != SP) && (rm != SP), "SP should not be used in 32-bit cmp");
672 adds_w(ZR, rn, rm);
684 void mnemonic(Register rd, Register rn, Register rm) { \
686 rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
701 void mnemonic(Register rd, Register rn, Register rm, int lsb) { \
704 lsb << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
738 void mnemonic(Register rn, int imm, int nzcv, AsmCondition cond) { \
742 cond << 12 | 1 << 11 | rn->encoding_with_zr() << 5 | nzcv); \
752 void mnemonic(Register rn, Register rm, int nzcv, AsmCondition cond) { \
755 cond << 12 | rn->encoding_with_zr() << 5 | nzcv); \
765 void mnemonic(Register rd, Register rn, Register rm, AsmCondition cond) { \
767 cond << 12 | op2 << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
797 void cinc(Register rd, Register rn, AsmCondition cond) {
798 csinc(rd, rn, rn, inverse(cond));
801 void cinc_w(Register rd, Register rn, AsmCondition cond) {
802 csinc_w(rd, rn, rn, inverse(cond));
805 void cinv(Register rd, Register rn, AsmCondition cond) {
806 csinv(rd, rn, rn, inverse(cond));
809 void cinv_w(Register rd, Register rn, AsmCondition cond) {
810 csinv_w(rd, rn, rn, inverse(cond));
814 void mnemonic(Register rd, Register rn) { \
816 rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
834 void mnemonic(Register rd, Register rn, Register rm) { \
836 opcode << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
855 void mnemonic(Register rd, Register rn, Register rm, Register ra) { \
857 o0 << 15 | ra->encoding_with_zr() << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
871 void mul(Register rd, Register rn, Register rm) {
872 madd(rd, rn, rm, ZR);
875 void mul_w(Register rd, Register rn, Register rm) {
876 madd_w(rd, rn, rm, ZR);
880 void mnemonic(Register rd, Register rn, Register rm) { \
882 o0 << 15 | 0b11111 << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
911 void mnemonic(Register rd, Register rn, int immr, int imms) { \
915 imms << 10 | rn->encoding_with_zr() << 5 | rd->encoding_with_zr()); \
928 void alias(Register rd, Register rn, int lsb, int width) { \
931 mnemonic(rd, rn, immr, imms); \
949 void alias(Register rd, Register rn, int shift) { \
951 mnemonic(rd, rn, immr, imms); \
963 void alias(Register rd, Register rn) { \
964 mnemonic(rd, rn, immr, imms); \
981 void mnemonic(Register rn) { \
982 emit_int32(0b1101011 << 25 | op << 21 | 0b11111 << 16 | rn->encoding_with_zr() << 5); \
1106 void mnemonic(FloatRegister rn, FloatRegister rm) { \
1108 rm->encoding() << 16 | 0b1000 << 10 | rn->encoding() << 5 | opcode2); \
1118 void mnemonic(FloatRegister rn) { \
1120 0b1000 << 10 | rn->encoding() << 5 | opcode2); \
1130 void mnemonic(FloatRegister rn, FloatRegister rm, int nzcv, AsmCondition cond) { \
1133 rm->encoding() << 16 | cond << 12 | 0b01 << 10 | rn->encoding() << 5 | op << 4 | nzcv); \
1143 void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm, AsmCondition cond) { \
1145 rm->encoding() << 16 | cond << 12 | 0b11 << 10 | rn->encoding() << 5 | rd->encoding()); \
1153 void mnemonic(FloatRegister rd, FloatRegister rn) { \
1155 opcode << 15 | 0b10000 << 10 | rn->encoding() << 5 | rd->encoding()); \
1191 void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm) { \
1193 rm->encoding() << 16 | opcode << 12 | 0b10 << 10 | rn->encoding() << 5 | rd->encoding()); \
1218 void mnemonic(FloatRegister rd, FloatRegister rn, FloatRegister rm, FloatRegister ra) { \
1220 o0 << 15 | ra->encoding() << 10 | rn->encoding() << 5 | rd->encoding()); \
1246 void mnemonic(Register rd, FloatRegister rn) { \
1248 rmode << 19 | opcode << 16 | rn->encoding() << 5 | rd->encoding_with_zr()); \
1301 void mnemonic(FloatRegister rd, Register rn) { \
1303 rmode << 19 | opcode << 16 | rn->encoding_with_zr() << 5 | rd->encoding()); \