aarch64/vm/c1_LIRAssembler_aarch64.cpp

166   jlong result;
169     result = (data->as_jint());
172     result = (data->as_jlong());
176     result = 0;  // unreachable
178   return result;
533 void LIR_Assembler::return_op(LIR_Opr result) {
534   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
1431         // result is a boolean
1442       // result is a boolean
1534     // result is a boolean
1623 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1639   assert(result->is_single_cpu() || result->is_double_cpu(),
1640          "expect single register for result");
1646       __ cset(result->as_register(), ncond);
1649       __ cset(result->as_register(), acond);
1659       __ cset(result->as_register_lo(), ncond);
1662       __ cset(result->as_register_lo(), acond);
1668     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1678     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1687   if (result->type() == T_LONG)
1688     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1690     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1895 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { Unimplemented(); }
2654   assert(op->result_opr()->is_single_cpu(), "result must be register");
2836     assert(dest->is_single_cpu(), "expect single result reg");
2839     assert(dest->is_double_cpu(), "expect double result reg");
2842     assert(dest->is_single_fpu(), "expect single float result reg");
2846     assert(dest->is_double_fpu(), "expect double float result reg");
2857 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2867     if (! result->is_illegal()) {
2868       switch (result->type()) {