Lines Matching refs:r22
84 __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28
120 __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000
169 __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16
274 __ ldarw(r22, r2); // ldar w22, [x2]
286 __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22]
290 __ ldarb(r22, r29); // ldarb w22, [x29]
299 __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
312 __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3]
321 __ strs(v13, Address(r22, 21)); // str s13, [x22, 21]
336 __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]!
352 __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4
355 __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51
363 __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0]
376 __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2]
390 __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887]
429 __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1
455 __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE
463 __ clsw(r24, r22); // cls w24, w22
466 __ rev32(r9, r22); // rev32 x9, x22
469 __ cls(r25, r22); // cls x25, x22
534 __ scvtfws(v28, r22); // scvtf s28, w22
551 __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96]
573 __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128]
574 __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176]