Lines Matching defs:opc
848 int opc;
868 opc = VexOpcode.VEX_OPCODE_0F;
871 opc = VexOpcode.VEX_OPCODE_0F_38;
874 opc = VexOpcode.VEX_OPCODE_0F_3A;
877 opc = VexOpcode.VEX_OPCODE_NONE;
882 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
884 encode = asm.simdPrefixAndEncode(dst, dst, src, pre, opc, attributes);
925 int opc;
945 opc = VexOpcode.VEX_OPCODE_0F;
948 opc = VexOpcode.VEX_OPCODE_0F_38;
951 opc = VexOpcode.VEX_OPCODE_0F_3A;
954 opc = VexOpcode.VEX_OPCODE_NONE;
958 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
960 asm.simdPrefix(dst, dst, src, pre, opc, attributes);
1011 int opc;
1031 opc = VexOpcode.VEX_OPCODE_0F;
1034 opc = VexOpcode.VEX_OPCODE_0F_38;
1037 opc = VexOpcode.VEX_OPCODE_0F_3A;
1040 opc = VexOpcode.VEX_OPCODE_NONE;
1044 encode = asm.simdPrefixAndEncode(dst, nds, src, pre, opc, attributes);
1052 int opc;
1072 opc = VexOpcode.VEX_OPCODE_0F;
1075 opc = VexOpcode.VEX_OPCODE_0F_38;
1078 opc = VexOpcode.VEX_OPCODE_0F_3A;
1081 opc = VexOpcode.VEX_OPCODE_NONE;
1084 asm.simdPrefix(dst, nds, src, pre, opc, attributes);
1150 int opc;
1170 opc = VexOpcode.VEX_OPCODE_0F;
1173 opc = VexOpcode.VEX_OPCODE_0F_38;
1176 opc = VexOpcode.VEX_OPCODE_0F_3A;
1179 opc = VexOpcode.VEX_OPCODE_NONE;
1184 encode = asm.simdPrefixAndEncode(src, Register.None, dst, pre, opc, attributes);
1186 encode = asm.simdPrefixAndEncode(src, src, dst, pre, opc, attributes);
1209 int opc;
1229 opc = VexOpcode.VEX_OPCODE_0F;
1232 opc = VexOpcode.VEX_OPCODE_0F_38;
1235 opc = VexOpcode.VEX_OPCODE_0F_3A;
1238 opc = VexOpcode.VEX_OPCODE_NONE;
1241 asm.simdPrefix(src, Register.None, dst, pre, opc, attributes);
1377 int opc;
1396 opc = VexOpcode.VEX_OPCODE_0F;
1399 opc = VexOpcode.VEX_OPCODE_0F_38;
1402 opc = VexOpcode.VEX_OPCODE_0F_3A;
1405 opc = VexOpcode.VEX_OPCODE_NONE;
1410 encode = asm.simdPrefixAndEncode(dst, Register.None, src, pre, opc, attributes);
1412 encode = asm.simdPrefixAndEncode(dst, dst, src, pre, opc, attributes);
1440 int opc;
1459 opc = VexOpcode.VEX_OPCODE_0F;
1462 opc = VexOpcode.VEX_OPCODE_0F_38;
1465 opc = VexOpcode.VEX_OPCODE_0F_3A;
1468 opc = VexOpcode.VEX_OPCODE_NONE;
1473 asm.simdPrefix(dst, Register.None, src, pre, opc, attributes);
1475 asm.simdPrefix(dst, dst, src, pre, opc, attributes);
2938 private void vexPrefix(int rxb, int ndsEncoding, int pre, int opc, AMD64InstructionAttr attributes) {
2942 if (isXorB || vexW || (opc == VexOpcode.VEX_OPCODE_0F_38) || (opc == VexOpcode.VEX_OPCODE_0F_3A)) {
2946 byte1 = ((~byte1) & 0xE0) | opc;
2963 private void vexPrefix(AMD64Address adr, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
2966 vexPrefix(rxb, ndsEncoding, pre, opc, attributes);
2970 private int vexPrefixAndEncode(Register dst, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
2973 vexPrefix(rxb, ndsEncoding, pre, opc, attributes);
2978 private void simdPrefix(Register xreg, Register nds, AMD64Address adr, int pre, int opc, AMD64InstructionAttr attributes) {
2980 vexPrefix(adr, nds, xreg, pre, opc, attributes);
2998 switch (opc) {
3014 private int simdPrefixAndEncode(Register dst, Register nds, Register src, int pre, int opc, AMD64InstructionAttr attributes) {
3016 return vexPrefixAndEncode(dst, nds, src, pre, opc, attributes);
3037 switch (opc) {