Lines Matching defs:to
16 * 2 along with this work; if not, write to the Free Software Foundation,
79 // Call stubs are used to call Java from C
306 // complete return to VM
369 // jump to exception handler
428 // If the compiler needs all registers to be preserved between the fault
436 // Note that we generate only this stub into a RuntimeStub, because it needs to be
457 // which has the ability to fetch the return PC out of thread-local storage
472 if (VerifyThread) __ mov(G2_thread, O0); // about to be smashed; pass early
527 // put addr in L0, then load through L0 to F0
529 __ set((intptr_t)&one, L0); __ ldf( FloatRegisterImpl::S, L0, 0, F1); // 1.0 to F1
531 // use add to put 2..18 in F2..F18
540 // use add to put 20..32 in F20..F32
604 // prefers to work with just one kind of synch. instruction.
609 // try to replace O2 with O3
614 __ delayed()->mov(O2, O0); // report previous value to caller
745 __ ret(); // Result in Rret is zero; flags set to Z
751 __ ret(); // Result in Rret is != 0; flags set to NZ
806 const Register to = O1;
808 const Register to_from = O3; // to - from
811 __ subcc(to, from, to_from);
907 // Use two shifts to clear out those low order two bits! (Cannot opt. into 1.)
930 typedef void (StubGenerator::*CopyLoopFunc)(Register from, Register to, Register count, int count_dec,
933 void disjoint_copy_core(Register from, Register to, Register count, int log2_elem_size,
942 prefetch_dist = (prefetch_dist + (iter_size-1)) & (-iter_size); // round up to one iteration copy size
955 // to <= from || to >= from+count
956 // but BIS will stomp over 'from' if (to > from-tail_size && to <= from)
957 __ sub(from, to, O4);
962 // BIS should not be used to copy tail (64 bytes+iter_size)
963 // to avoid zeroing of following values.
966 if (prefetch_count > 0) { // rounded up to one iteration count
973 (this->*copy_loop_func)(from, to, count, count_dec, L_block_copy_prefetch, true, true);
979 (this->*copy_loop_func)(from, to, count, count_dec, L_block_copy, false, true);
991 if (prefetch_count > 0) { // rounded up to one iteration count
999 (this->*copy_loop_func)(from, to, count, count_dec, L_copy_prefetch, true, false);
1005 (this->*copy_loop_func)(from, to, count, count_dec, L_copy, false, false);
1013 void copy_16_bytes_shift_loop(Register from, Register to, Register count, int count_dec,
1026 __ prefetch(to, ArraycopyDstPrefetchDistance, Assembler::severalWritesAndPossiblyReads);
1031 __ inc(to, 16);
1040 __ stxa(O3, to, -16);
1041 __ stxa(O4, to, -8);
1043 __ stx(O3, to, -16);
1044 __ stx(O4, to, -8);
1054 // to - destination array aligned to 8-bytes
1055 // count - elements count to copy >= the count equivalent to 16 bytes
1056 // count_dec - elements count's decrement equivalent to 16 bytes
1059 void copy_16_bytes_forward_with_shift(Register from, Register to,
1079 // to form 2 aligned 8-bytes chunks to store.
1087 disjoint_copy_core(from, to, count, log2_elem_size, 16, &StubGenerator::copy_16_bytes_shift_loop);
1095 __ inc(to, 8);
1099 __ stx(G3, to, -8);
1113 // end_to - destination array end address aligned to 8-bytes
1114 // count - elements count to copy >= the count equivalent to 16 bytes
1115 // count_dec - elements count's decrement equivalent to 16 bytes
1138 // to form 2 aligned 8-bytes chunks to store.
1181 // "from" and "to" addresses are assumed to be heapword aligned.
1185 // to: O1
1197 const Register to = O1; // destination array address
1217 // of this arraycopy call site that both 'from' and 'to' addresses
1224 // copy bytes to align 'to' on 8 byte boundary
1225 __ andcc(to, 7, G1); // misaligned bytes
1228 __ inc(G1, 8); // bytes need to copy to next 8-bytes alignment
1234 __ stb(O3, to, 0);
1236 __ delayed()->inc(to);
1241 // the same alignment mod 8, otherwise fall through to the next
1246 copy_16_bytes_forward_with_shift(from, to, count, 0, L_copy_byte);
1262 __ stb(O3, to, offset);
1276 // "from" and "to" addresses are assumed to be heapword aligned.
1280 // to: O1
1295 const Register to = O1; // destination array address
1298 const Register end_to = to; // destination array end address
1310 __ add(to, count, end_to); // offset after last copied element
1321 // copy bytes to align 'end_to' on 8 byte boundary
1336 // Both arrays are aligned to 8-bytes in 64-bits VM.
1342 // the same alignment mod 8, otherwise jump to the next
1385 // "from" and "to" addresses are assumed to be heapword aligned.
1389 // to: O1
1401 const Register to = O1; // destination array address
1421 // of this arraycopy call site that both 'from' and 'to' addresses
1428 // copy 1 element if necessary to align 'to' on an 4 bytes
1429 __ andcc(to, 3, G0);
1433 __ inc(to, 2);
1435 __ sth(O3, to, -2);
1438 // copy 2 elements to align 'to' on an 8 byte boundary
1439 __ andcc(to, 7, G0);
1445 __ inc(to, 4);
1446 __ sth(O3, to, -4);
1447 __ sth(O4, to, -2);
1452 // the same alignment mod 8, otherwise fall through to the next
1457 copy_16_bytes_forward_with_shift(from, to, count, 1, L_copy_2_bytes);
1473 __ sth(O3, to, offset);
1487 // "to" address is assumed to be heapword aligned.
1490 // to: O0
1499 const Register to = O0; // source array address
1549 __ andcc(to, 1, G0);
1552 __ stb(value, to, 0);
1553 __ inc(to, 1);
1558 __ andcc(to, 2, G0);
1561 __ sth(value, to, 0);
1562 __ inc(to, 2);
1567 // align to 8 bytes, we know we are 4 byte aligned to start
1568 __ andcc(to, 7, G0);
1571 __ stw(value, to, 0);
1572 __ inc(to, 4);
1596 __ stx(value, to, 0);
1597 __ stx(value, to, 8);
1598 __ stx(value, to, 16);
1599 __ stx(value, to, 24);
1603 __ delayed()->add(to, 32, to);
1617 __ stx(value, to, 0);
1620 __ delayed()->add(to, 8, to);
1634 __ stw(value, to, 0);
1636 __ inc(to, 4);
1642 __ sth(value, to, 0);
1644 __ inc(to, 2);
1650 __ stb(value, to, 0);
1668 __ stb(value, to, 0);
1669 __ inc(to, 1);
1673 __ stb(value, to, 0);
1674 __ stb(value, to, 1);
1675 __ inc(to, 2);
1679 __ stb(value, to, 0);
1680 __ stb(value, to, 1);
1681 __ stb(value, to, 2);
1683 __ delayed()->stb(value, to, 3);
1692 __ sth(value, to, 0);
1693 __ inc(to, 2);
1697 __ sth(value, to, 0);
1699 __ delayed()->sth(value, to, 2);
1706 // "from" and "to" addresses are assumed to be heapword aligned.
1710 // to: O1
1725 const Register to = O1; // destination array address
1728 const Register end_to = to; // destination array end address
1730 const Register byte_count = O3; // bytes count to copy
1743 __ add(to, byte_count, end_to); // offset after last copied element
1754 // copy 1 element if necessary to align 'end_to' on an 4 bytes
1764 // copy 2 elements to align 'end_to' on an 8 byte boundary
1777 // Both arrays are aligned to 8-bytes in 64-bits VM.
1783 // the same alignment mod 8, otherwise jump to the next
1826 void copy_16_bytes_loop(Register from, Register to, Register count, int count_dec,
1836 __ prefetch(to, ArraycopyDstPrefetchDistance, Assembler::severalWritesAndPossiblyReads);
1841 __ inc(to, 16);
1851 __ stxa(O3, to, -16);
1852 __ stxa(O4, to, -8);
1854 __ stx(O3, to, -16);
1855 __ stx(O4, to, -8);
1864 // If "aligned" is true, the "from" and "to" addresses are assumed
1865 // to be heapword aligned.
1869 // to: O1
1878 const Register to = O1; // destination array address
1884 // of this arraycopy call site that both 'from' and 'to' addresses
1899 // copy 1 element to align 'to' on an 8 byte boundary
1900 __ andcc(to, 7, G0);
1904 __ inc(to, 4);
1906 __ st(O3, to, -4);
1916 // to form 2 aligned 8-bytes chunks to store.
1925 disjoint_copy_core(from, to, count, 2, 16, &StubGenerator::copy_16_bytes_loop);
1945 __ st(O3, to, offset);
1953 // "from" and "to" addresses are assumed to be heapword aligned.
1957 // to: O1
1985 // If "aligned" is true, the "from" and "to" addresses are assumed
1986 // to be heapword aligned.
1990 // to: O1
2000 const Register to = O1; // destination array address
2003 const Register end_to = to; // destination array end address
2006 const Register byte_count = O3; // bytes count to copy
2009 __ add(to, byte_count, end_to); // offset after last copied element
2015 // copy 1 element to align 'to' on an 8 byte boundary
2034 // to form 2 aligned 8-bytes chunks to store.
2086 // "from" and "to" addresses are assumed to be heapword aligned.
2090 // to: O1
2121 void copy_64_bytes_loop(Register from, Register to, Register count, int count_dec,
2131 __ prefetch(to, ArraycopyDstPrefetchDistance+off, Assembler::severalWritesAndPossiblyReads);
2137 __ stxa(O4, to, off+0);
2138 __ stxa(O5, to, off+8);
2140 __ stx(O4, to, off+0);
2141 __ stx(O5, to, off+8);
2147 __ delayed()->inc(to, 64);
2157 // to: O1
2184 const Register to = O1; // destination array address
2200 __ delayed()->mov(to, to64);
2220 __ stx(O3, to, offset0);
2222 __ stx(G3, to, offset8);
2232 __ stx(O3, to, offset0);
2243 // to: O1
2275 // to: O1
2282 const Register to = O1; // destination array address
2295 __ stx(O2, to, offset8);
2297 __ stx(O3, to, offset0);
2305 __ stx(O3, to, 0);
2315 // to: O1
2346 // "from" and "to" addresses are assumed to be heapword aligned.
2350 // to: O1
2357 const Register to = O1; // destination array address
2373 __ mov(to, G1);
2393 // "from" and "to" addresses are assumed to be heapword aligned.
2397 // to: O1
2405 const Register to = O1; // destination array address
2423 __ mov(to, G1);
2484 // to: O1
2519 // otherwise, we would have to make conjoint checks
2543 // Empty array: Nothing to do.
2559 __ inc(O5_offset, heapOopSize); // step to next offset
2571 // branch to this on success:
2575 // It was a real error; we must depend on the caller to finish the job.
2578 // and report their number to the caller.
2582 __ delayed()->not1(O2_count, O0); // report (-1^K) to caller
2602 // to: O1
2606 // to a long, int, short, or byte copy loop.
2685 // Have to clean up high 32-bits of 'src_pos' and 'dst_pos'.
2706 // O0 == -1 - need to call System.arraycopy
2743 // Assembler stubs will be used for this call to arraycopy
2809 // Load 32-bits signed value. Use br() instruction with it to check icc.
2833 // At this point, it is known to be a typeArray (array_tag 0x3).
2846 __ delayed(); // match next insn to prev branch
2867 // next registers should be set before the jump to corresponding stub
2869 const Register to = O1; // destination array address
2872 // 'from', 'to', 'count' registers should be set in this order
2875 BLOCK_COMMENT("scale indexes to element size");
2879 __ add(dst, dst_pos, to); // dst_addr
2922 __ add(dst, dst_pos, to); // dst_addr
2931 // lduw(G4_dst_klass, lh_offset, O5_temp); // hoisted to delay slot
2935 // It is safe to examine both src.length and dst.length.
2936 __ delayed(); // match next insn to prev branch
2946 __ add(dst, dst_pos, to); // dst_addr
2950 assert_different_registers(from, to, count, sco_temp,
2978 // "to" address is aligned to jlong (8 bytes).
2981 // to: O0
2990 const Register to = O0; // source array address
2995 __ sllx(count, LogHeapWordSize, count); // to bytes count
2997 __ bis_zeroing(to, count, temp, Ldone);
3044 // entry_jint_arraycopy always points to the unaligned version (notice that we overwrite it).
3127 "the following code assumes that first element of an int array is aligned to 8 bytes");
3133 Register to = O1; // destination byte array
3140 // Method to address arbitrary alignment for load instructions:
3141 // Check last 3 bits of 'from' address to see if it is aligned to 8-byte boundary
3143 // If not zero/mis-aligned then alignaddr will set GSR.align with number of bytes to skip during faligndata
3144 // alignaddr will also convert arbitrary aligned 'from' address to nearest 8-byte aligned address
3145 // load 3 * 8-byte components (to read 16 bytes input) in 3 different FP regs starting at this aligned address
3217 // Method to address arbitrary alignment for store instructions:
3218 // Check last 3 bits of 'dest' address to see if it is aligned to 8-byte boundary
3224 // Set GSR.align to (8-n) using alignaddr
3226 // Set the arbitrarily aligned 'dest' address to nearest 8-byte aligned address
3229 // We need to execute this process for both the 8-byte result values
3232 __ andcc(to, 7, O5);
3234 __ delayed()->edge8n(to, G0, O3);
3237 __ stf(FloatRegisterImpl::D, F54, to, 0);
3239 __ delayed()->stf(FloatRegisterImpl::D, F56, to, 8);
3242 __ add(to, 8, O4);
3248 __ and3(to, -8, to);
3250 __ stpartialf(to, O3, F54, Assembler::ASI_PST8_PRIMARY);
3252 __ add(to, 8, to);
3255 __ stpartialf(to, O3, F54, Assembler::ASI_PST8_PRIMARY);
3264 "the following code assumes that first element of an int array is aligned to 8 bytes");
3267 "the following code assumes that first element of a byte array is aligned to 8 bytes");
3274 Register to = O1; // destination byte array
3282 // save 'from' since we may need to recheck alignment in case of 256-bit decryption
3424 __ andcc(to, 7, O5);
3426 __ delayed()->edge8n(to, G0, O3);
3429 __ stf(FloatRegisterImpl::D, F52, to, 0);
3431 __ delayed()->stf(FloatRegisterImpl::D, F54, to, 8);
3434 __ add(to, 8, O4);
3440 __ and3(to, -8, to);
3442 __ stpartialf(to, O3, F52, Assembler::ASI_PST8_PRIMARY);
3444 __ add(to, 8, to);
3447 __ stpartialf(to, O3, F52, Assembler::ASI_PST8_PRIMARY);
3456 "the following code assumes that first element of an int array is aligned to 8 bytes");
3458 "the following code assumes that first element of a byte array is aligned to 8 bytes");
3467 Register to = I1; // destination byte array
3474 // save cipher len to return in the end
3555 __ andcc(to, 7, L1);
3557 __ delayed()->edge8n(to, G0, L2);
3560 __ stf(FloatRegisterImpl::D, F60, to, 0);
3561 __ stf(FloatRegisterImpl::D, F62, to, 8);
3565 __ add(to, 8, L3);
3570 // as it needs to be stored as iv for next block (see code before next retl)
3575 __ mov(to, L5);
3576 __ and3(to, -8, to);
3578 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3580 __ add(to, 8, to);
3583 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3585 __ mov(L5, to);
3591 __ add(to, 16, to);
3648 __ andcc(to, 7, L1);
3650 __ delayed()->edge8n(to, G0, L2);
3653 __ stf(FloatRegisterImpl::D, F60, to, 0);
3654 __ stf(FloatRegisterImpl::D, F62, to, 8);
3658 __ add(to, 8, L3);
3666 __ mov(to, L5);
3667 __ and3(to, -8, to);
3669 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3671 __ add(to, 8, to);
3674 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3676 __ mov(L5, to);
3683 __ add(to, 16, to);
3741 __ andcc(to, 7, L1);
3743 __ delayed()->edge8n(to, G0, L2);
3746 __ stf(FloatRegisterImpl::D, F60, to, 0);
3747 __ stf(FloatRegisterImpl::D, F62, to, 8);
3751 __ add(to, 8, L3);
3759 __ mov(to, L5);
3760 __ and3(to, -8, to);
3762 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3764 __ add(to, 8, to);
3767 __ stpartialf(to, L2, F60, Assembler::ASI_PST8_PRIMARY);
3769 __ mov(L5, to);
3776 __ add(to, 16, to);
3791 "the following code assumes that first element of an int array is aligned to 8 bytes");
3793 "the following code assumes that first element of a byte array is aligned to 8 bytes");
3805 Register to = I1; // destination byte array
3813 // save cipher len to return in the end
3966 __ andcc(to, 7, G1);
3968 __ delayed()->edge8n(to, G0, G2);
3971 __ stf(FloatRegisterImpl::D, F60, to, 0);
3972 __ stf(FloatRegisterImpl::D, F62, to, 8);
3976 __ add(to, 8, G3);
3982 __ mov(to, G1);
3983 __ and3(to, -8, to);
3985 __ stpartialf(to, G2, F60, Assembler::ASI_PST8_PRIMARY);
3987 __ add(to, 8, to);
3990 __ stpartialf(to, G2, F60, Assembler::ASI_PST8_PRIMARY);
3992 __ mov(G1, to);
3996 __ add(to, 16, to);
4086 // parts that need to be stored starting at mis-aligned address are in a FP reg
4088 // we then use the edge + partial-store mechanism to store the 'head' and 'tail' parts
4091 __ andcc(to, 7, G1);
4093 __ delayed()->edge8n(to, G0, G2);
4096 __ stf(FloatRegisterImpl::D, F40, to, 0);
4097 __ stf(FloatRegisterImpl::D, F42, to, 8);
4098 __ stf(FloatRegisterImpl::D, F60, to, 16);
4099 __ stf(FloatRegisterImpl::D, F62, to, 24);
4110 __ mov(to, G1);
4111 __ and3(to, -8, to);
4112 __ stpartialf(to, G2, F40, Assembler::ASI_PST8_PRIMARY);
4113 __ stf(FloatRegisterImpl::D, F56, to, 8);
4114 __ stf(FloatRegisterImpl::D, F42, to, 16);
4115 __ stf(FloatRegisterImpl::D, F60, to, 24);
4116 __ add(to, 32, to);
4118 __ stpartialf(to, G2, F40, Assembler::ASI_PST8_PRIMARY);
4119 __ mov(G1, to);
4123 __ add(to, 32, to);
4207 __ andcc(to, 7, G1);
4209 __ delayed()->edge8n(to, G0, G2);
4212 __ stf(FloatRegisterImpl::D, F48, to, 0);
4213 __ stf(FloatRegisterImpl::D, F50, to, 8);
4214 __ stf(FloatRegisterImpl::D, F60, to, 16);
4215 __ stf(FloatRegisterImpl::D, F62, to, 24);
4226 __ mov(to, G1);
4227 __ and3(to, -8, to);
4228 __ stpartialf(to, G2, F48, Assembler::ASI_PST8_PRIMARY);
4229 __ stf(FloatRegisterImpl::D, F56, to, 8);
4230 __ stf(FloatRegisterImpl::D, F50, to, 16);
4231 __ stf(FloatRegisterImpl::D, F60, to, 24);
4232 __ add(to, 32, to);
4234 __ stpartialf(to, G2, F48, Assembler::ASI_PST8_PRIMARY);
4235 __ mov(G1, to);
4239 __ add(to, 32, to);
4347 __ andcc(to, 7, G1);
4349 __ delayed()->edge8n(to, G0, G2);
4352 __ stf(FloatRegisterImpl::D, F0, to, 0);
4353 __ stf(FloatRegisterImpl::D, F2, to, 8);
4354 __ stf(FloatRegisterImpl::D, F60, to, 16);
4355 __ stf(FloatRegisterImpl::D, F62, to, 24);
4366 __ mov(to, G1);
4367 __ and3(to, -8, to);
4368 __ stpartialf(to, G2, F0, Assembler::ASI_PST8_PRIMARY);
4369 __ stf(FloatRegisterImpl::D, F56, to, 8);
4370 __ stf(FloatRegisterImpl::D, F2, to, 16);
4371 __ stf(FloatRegisterImpl::D, F60, to, 24);
4372 __ add(to, 32, to);
4374 __ stpartialf(to, G2, F0, Assembler::ASI_PST8_PRIMARY);
4375 __ mov(G1, to);
4379 __ add(to, 32, to);
4427 __ mov(ofs, O0); // to be returned
4453 __ mov(ofs, O0); // to be returned
4498 __ mov(ofs, O0); // to be returned
4524 __ mov(ofs, O0); // to be returned
4569 __ mov(ofs, O0); // to be returned
4595 __ mov(ofs, O0); // to be returned
4642 // Align to read 'data'
4793 // Max number of bytes we can process before having to take the mod
4803 // s1 is initialized to the lower 16 bits of adler
4804 // s2 is initialized to the upper 16 bits of adler
4810 // It does check this, but it is more effective to skip to the cleanup loop
4814 // Check if we are above the cutoff, if not go to the cleanup loop immediately
4822 // Loop maintenance stuff is done at the end of the loop, so skip to there
4838 // to be processed by the outter loop
4850 // Original temp 0-7 used and new loads to temp 0-7 issued
4851 // temp 8-15 ready to be consumed
4895 // Make sure there is something left to process
4914 // There might be nothing left to process
4983 // Note: This is code that could be shared among different platforms - however the benefit seems to be smaller than
5025 // These entry points require SharedInfo::stack0 to be set up in non-core builds
5103 // put extra information in the stub code, to make it more readable