s390/vm/macroAssembler_s390.cpp

561   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
572   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
583   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
598 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
638 // imm == 0 emits either no instruction or r1 := r2 !
640 //           instruction sequences are required!!!
682       // Always use LAY instruction, so we don't need the tmp register.
906 // Implementation on x86/sparc assumes that constant and instruction section are
1029 // Return len (in bytes) of generated instruction(s).
1031 // set_cc:    Use instruction that sets the condition code, if true.
1100   // which issues an unnecessary add instruction.
1310 //  Extract the constant from a load_constant instruction stream.
1721       // No instruction with immediate operand possible, so load into register.
1842 // Patch instruction `inst' at offset `inst_pos' to refer to `dest_pos'
1843 // and return the resulting instruction.
1887     print_dbg_msg(tty, inst,         "<- original instruction: branch patching error", 0);
1888     print_dbg_msg(tty, patched_inst, "<- patched  instruction: branch patching error", 0);
1924   print_dbg_msg(tty, inst, "not a pcrelative instruction", 6);
1946     dump_code_range(tty, pc, 32, "not a pcrelative instruction");
1961   assert(is_pcrelative_long(pc), "not a pcrelative instruction");
1997   guarantee(false, "not a pcrelative instruction to patch!");
2000 // "Current PC" here means the address just behind the basr instruction.
2002   z_basr(result, Z_R0); // Don't branch, just save next instruction address in result.
2008 // "Current PC" here means the address of the larl instruction plus the given offset.
2011   z_larl(result, offset/2); // Save target instruction address in result.
2387 // Identify a call_far_patchable instruction: LARL + LG + BASR
2391 //    basr Z_R14,rx         ; end of this instruction must be aligned to a word boundary
2398   // Check for the actual load instruction.
2402   // Check for the call (BASR) instruction, finally.
2407 // Identify a call_far_patchable instruction: BRASL
2424   // --> Check for call instruction.
2448 //  - BRASL                  (relative address of call target coded in instruction)
2450 // by leading nops, such that the instruction sequence always ends at the same
2452 // Furthermore, the return address (the end of the instruction sequence) is forced
2522 // Identify a call_far_patchable instruction.
2529 // Does the call_far_patchable instruction use a pc-relative encoding
2541 // Set destination address of a call_far_patchable instruction.
2553 // Get dest address of a call_far_patchable instruction.
2558   // Relative address encoded in call instruction.
2592 // Use TM or TMY instruction, depending on read offset.
2636 // Extract poll address from instruction and ucontext.
2659 // Extract poll register from instruction.
2674 bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
3863   assert(Immediate::is_uimm16(_thread_max_state), "enum value out of range for instruction");
3934   // the proper beginning of the next instruction.
4030   // the proper beginning of the next instruction.
4077   // the proper beginning of the next instruction.
4273 // maybeNULLtarget - Branch target for Rop1 == NULL, if flow control shall NOT continue with compare instruction.
4499       // Don't use lay instruction.
4795 // MVCLE instruction automatically exploits H/W-optimized page mover.
5255     // Use clc instruction for up to 256 bytes.
5282     // Use clcle instruction.
5605 // If the instruction sequence at the given pc is a load_const_from_toc
5625 // If the instruction sequence at the given pc is a load_const_from_toc
5637     assert((cb == NULL) || (nm == (nmethod*)cb), "instruction address should be in CodeBlob");
5658 //  inspection of generated instruction sequences for a particular pattern
5715   assert(VM_Version::has_ETF2(), "instruction must be available");
5736   assert(VM_Version::has_ETF3(), "instruction must be available");
6739   // the proper beginning of the next instruction.
6740   z_illtrap(); // Illegal instruction.
6741   z_illtrap(); // Illegal instruction.
6780     z_illtrap(); // Illegal instruction as emergency stop, should the above call return.